Sandisk’s New Patent Puts HBM and NAND Side-by-Side on One Interposer

Executive Summary

Sandisk’s US Patent 12,430,274 B2 describes a striking approach to AI package design. Instead of treating NAND flash as a remote storage device, the architecture places a multicore processor directly over a high-capacity non-volatile memory tile built with CMOS Bonded to Array technology. The combined processor-and-NAND structure is mounted on an interposer, while one or more High Bandwidth Memory stacks sit around it on the same interposer.

The popular description that Sandisk is putting “HBM and NAND side-by-side” is directionally correct but incomplete. The more important innovation is vertical: compute may be directly bonded above a NAND-and-logic tile. Horizontally, HBM stacks remain connected through the shared interposer. The result is a heterogeneous package containing three complementary resources—compute, fast DRAM, and dense persistent flash.

This design does not prove that Sandisk plans to manufacture a commercial GPU, nor does a granted patent guarantee that the architecture will become a product. It does, however, reveal a credible long-term direction. AI inference increasingly requires more model capacity than economical HBM configurations can provide. Conventional SSDs offer capacity but remain too far from the processor. Sandisk’s proposal attempts to close that physical and architectural gap.

The strategic conclusion: the patent is not an argument that NAND will replace HBM. It is a blueprint for making HBM a specialized hot-memory tier while NAND becomes a much larger near-compute model tier. If packaging, thermal, software, endurance, and manufacturing challenges can be solved, this type of architecture could reduce accelerator count, data movement, and cost per AI token.

01 · Patent Overview

What Sandisk’s Patent Actually Describes

The patent at the center of the discussion is US 12,430,274 B2, titled around a processing core integrating high-capacity, high-bandwidth storage memory. Public reporting highlighted it in June 2026, although patent activity naturally begins before media attention. The disclosed architecture places a processor, which could include multiple processing cores, directly over a non-volatile memory tile. That tile combines a large NAND array with a CMOS logic layer using a bonded structure.

The processor-and-memory assembly sits on an interposer. HBM stacks are positioned on one or more sides of the central structure and connect through that interposer. This arrangement gives the processor access to two fundamentally different external data resources within one package: low-latency, high-bandwidth DRAM and very high-capacity, non-volatile NAND.

The architectural language matters. Describing the design only as HBM and NAND sitting beside each other can create the impression of two conventional memory packages attached to a substrate. The patent is more ambitious. Its central compute die may be vertically aligned with and directly bonded to the NAND-based tile beneath it. HBM is the side-by-side component; NAND may be the under-processor component.

This creates a form of heterogeneous three-dimensional integration. Vertical connections can shorten the path between compute and the NAND control logic. Horizontal interposer connections can give the processor wide access to HBM. The package therefore combines vertical density with lateral bandwidth.

The patent does not require every commercial implementation to follow one fixed diagram. Patent documents commonly describe multiple embodiments, configurations, and alternatives. Some may use different numbers of memory tiles, HBM stacks, processing cores, or interconnect arrangements. The commercial significance lies in the broader principle: storage-class capacity is brought into the accelerator package rather than remaining behind an SSD controller elsewhere in the server.

The invention is best interpreted as an architectural exploration rather than a declaration that Sandisk intends to compete directly with established GPU vendors. A memory company can patent package structures for licensing, partnerships, joint products, defensive protection, or future strategic options. Accelerator providers, foundries, packaging companies, and hyperscalers could all participate in a practical implementation.

02 · Market Context

Why AI Needs a New Memory Hierarchy

The AI industry has spent years increasing mathematical throughput. Modern accelerators contain vast arrays of units optimized for matrix operations, reduced-precision arithmetic, and tensor processing. Yet those units cannot produce useful results without a continuous supply of data. As compute performance rises, moving data becomes a larger share of system cost, latency, and energy.

Large models intensify the challenge. A model with hundreds of billions of parameters may require hundreds of gigabytes even at reduced precision. Mixture-of-experts systems can contain far more total parameters, although only a portion is active for each token. Multimodal systems add vision, audio, and video components. Long-context models create large key-value caches, while retrieval systems require embeddings and indexes.

HBM provides the bandwidth needed to keep accelerators active, but its capacity is limited by DRAM density, stack height, package area, thermal requirements, yield, and cost. When a model does not fit into one accelerator’s memory, operators partition it across multiple devices. Communication among those devices introduces additional hardware, networking, synchronization, power, and latency.

Sometimes the system needs the compute power of several accelerators. In other cases, additional GPUs are purchased primarily for their attached HBM. That is economically inefficient. An operator is buying expensive arithmetic merely to obtain more memory capacity.

Conventional SSDs solve the capacity problem but not the proximity problem. They sit behind controllers and interfaces that were designed for block storage, compatibility, and persistence rather than direct tensor feeding. Even with technologies such as direct storage access, the path between NAND and the accelerator remains relatively long and narrow compared with HBM.

Host DRAM offers an intermediate tier, but it also communicates through external links and consumes server power and board area. CXL can create larger and more flexible memory pools, yet pooled memory is still farther from the accelerator than a co-packaged resource. Each tier involves a compromise among capacity, cost, bandwidth, latency, persistence, and programmability.

Sandisk’s patent responds by collapsing parts of that hierarchy into one package. The processor can retain immediate working data in HBM while accessing a much larger NAND pool beneath or immediately adjacent to it. If software can predict data needs and move tensors before execution stalls, the architecture may deliver a useful combination of HBM responsiveness and NAND capacity.

03 · Package Architecture

Inside the Processor-on-NAND Design

A useful way to understand the patent is to divide the proposed package into four functional zones: compute, hot memory, capacity memory, and interconnect.

Compute Zone

The processing component may contain multiple cores and could represent a GPU, AI accelerator, or another specialized processor. Its vertical placement above the non-volatile memory tile shortens the path to the logic controlling NAND. Direct bonding can provide many more connections than a conventional board-level interface.

Hot-Memory Zone

HBM stacks remain on the interposer beside the central compute assembly. They provide low-latency access for activations, rapidly updated cache data, intermediate results, metadata, frequently used model segments, and other information that NAND cannot serve efficiently.

Capacity-Memory Zone

The bonded NAND tile supplies a much larger pool for model weights, embeddings, cold experts, retrieval structures, or other mostly read-oriented data. Because NAND is non-volatile, the data may remain resident when the main system is powered down, subject to security and integrity policies.

Interconnect Zone

The interposer connects the compute die, HBM stacks, NAND control logic, and package I/O. It may carry wide data paths that would be impractical through standard circuit-board traces. The architecture can therefore reduce reliance on PCIe or another external storage path for model-weight movement.

These resources form a hardware-managed or software-managed hierarchy. The processor does not necessarily execute directly from raw NAND cells. Instead, data can move through controllers, buffers, caches, and HBM according to application requirements. A model layer might be prefetched from NAND while the preceding layer executes. Once transferred into HBM or local SRAM, it can be consumed with much lower latency.

Alternative policies are possible. Large tensor tiles could stream directly from the NAND subsystem into compute pipelines when access is predictable. Frequently reused tensors could stay in HBM. Sparse experts could be promoted according to observed popularity. Writes could be buffered and consolidated to protect flash endurance.

The architectural breakthrough is not that NAND suddenly performs like DRAM. It is that the package gives the system enough physical proximity, parallel connectivity, and scheduling knowledge to use each medium according to its strengths.

04 · NAND Technology

Why CMOS Bonded to Array Matters

CMOS Bonded to Array, commonly abbreviated as CBA, separates the memory array from the CMOS circuitry that controls it. The NAND array and peripheral logic can be manufactured on different wafers using processes optimized for their respective functions. They are then bonded together with dense connections.

This separation offers several potential benefits. Memory engineers can optimize the NAND structure for layer count, cell density, retention, and manufacturing yield. Logic engineers can optimize the controller-facing circuitry for speed, power, signal processing, and interface density. Neither portion must accept every compromise imposed by fabricating the entire device in one monolithic flow.

For Sandisk’s patent, the logic layer is especially important. The processor above the tile must not communicate with NAND as though it were a conventional SSD. The CMOS layer can provide scheduling, parallel channel access, error correction, buffering, address management, compression, security, and direct interfaces to the processor or interposer.

Dense hybrid bonding can create many vertical connections between the processor and the NAND logic. This reduces physical distance and may increase bandwidth per unit of package area. It also opens opportunities for workload-specific logic close to the data. Functions such as decompression, data filtering, address translation, integrity checking, sparse-tensor handling, and simple data movement operations might occur below the main processor.

That possibility introduces near-data processing. Instead of transporting every raw byte to the accelerator, the memory tile could transform or select data before transmission. For example, a compressed model representation might be decoded near the NAND array. A retrieval structure could discard irrelevant entries before sending results to the processor. Such operations could reduce interconnect traffic and energy.

However, greater logic capability increases design and manufacturing complexity. The CMOS tile consumes power and area, and advanced logic processes are expensive. Firmware becomes a critical part of system reliability. Designers must decide which functions belong in the memory logic, which remain in the accelerator, and how both components coordinate without creating bottlenecks.

CBA therefore makes the architecture plausible, but it does not automatically solve NAND latency. Individual flash reads remain slower than DRAM. The performance strategy still depends on parallelism, large transfers, prefetching, and caching.

05 · Interconnect

The Interposer Becomes the Memory Traffic Hub

An interposer is a high-density connectivity layer positioned between semiconductor dies and the package substrate. It enables far more connections and finer wiring than a conventional printed circuit board. In existing AI accelerators, interposers commonly connect a large compute die with several HBM stacks.

Sandisk’s concept gives the interposer a broader role. It must connect the processor-on-NAND assembly with HBM, package I/O, power-delivery structures, and potentially other chiplets. The interposer effectively becomes the local fabric for a heterogeneous memory system.

This arrangement can provide high bandwidth without routing every transaction through an external server interface. HBM traffic travels laterally across the interposer. NAND-related traffic may move vertically through the bonded structure or laterally through its logic tile, depending on the implementation. Data can theoretically flow between the memory tiers without making a round trip through host memory.

The interposer can also support modularity. A product family might vary the number of HBM stacks, the amount of NAND, or the compute chiplet while retaining a common platform. A training-oriented version could allocate more area to HBM. An inference version could use greater NAND capacity. An edge version might employ fewer stacks and a lower-power processor.

Yet interposer area is expensive, and reticle limits constrain the size of silicon interposers. Larger packages have lower yields, more demanding warpage control, and more difficult power delivery. Organic interposers, silicon bridges, fan-out packaging, and other approaches offer different cost and performance trade-offs.

Signal integrity also becomes challenging. HBM, NAND logic, chiplet links, and external interfaces generate different traffic patterns. Designers must prevent one workload from interfering with another. The package requires a quality-of-service mechanism so a large NAND transfer does not delay urgent HBM transactions.

In effect, the interposer is no longer passive wiring. Even if routing logic remains elsewhere, the package topology defines the performance of the entire memory hierarchy. Its area, bandwidth, thermal properties, and manufacturing yield will be central to commercial viability.

06 · Memory Hierarchy

Does the Patent Really Demote HBM?

Some headlines have characterized the patent as relegating HBM to a supporting role. That interpretation captures the shift in capacity emphasis but can undervalue HBM’s importance. In a heterogeneous package, a smaller memory tier can still determine overall performance.

HBM would likely hold the most active data: current activations, key-value cache segments, intermediate results, routing tables, frequently selected experts, write-intensive structures, and tensors that cannot tolerate NAND latency. It could also act as a cache for the larger NAND pool. Every high-performance operation may depend on HBM even when most stored bits reside in flash.

The change is therefore not from “important” to “unimportant.” It is from universal near-compute capacity to premium working memory. HBM becomes analogous to a high-speed desk, while NAND is a large bookshelf within arm’s reach. The bookshelf may contain far more information, but the desk remains essential for the material currently in use.

This division can make HBM more economically efficient. Today, operators sometimes need additional HBM simply to fit a model, even when parts of that model are cold or predictable. A NAND tier can absorb this capacity and reserve HBM for data whose behavior justifies its premium.

HBM suppliers may therefore benefit from the architecture. A system that uses HBF or bonded NAND can expand the market for AI inference accelerators, increasing the number of packages that still require HBM. Memory vendors with both DRAM and NAND capabilities could offer optimized combinations.

The amount of HBM required will depend on workload and software. A system with excellent prefetching may use a relatively small HBM cache. A low-latency service or dynamic mixture-of-experts model may need a larger pool. Product designers can tune the ratio rather than accepting one fixed memory architecture.

07 · Product Strategy

How the Patent Relates to Sandisk’s HBF Roadmap

Sandisk has separately promoted High Bandwidth Flash, or HBF, as a new near-compute memory category. HBF applies HBM-like parallelism and stacked packaging concepts to NAND. It seeks to provide much greater capacity than HBM while delivering enough aggregate bandwidth for AI inference.

In August 2026, Sandisk and SK hynix announced the first open HBF standard through the Open Compute Project. Public specifications described two stack configurations, capacity reaching 512 GB, three performance grades from approximately 0.4 TB/s to 3.0 TB/s, and a UCIe-based interface. These details represent an ecosystem-oriented and potentially nearer-term path to standardized HBF products.

The processor-on-NAND patent should not automatically be treated as the same product. Conventional HBF can exist as one or more high-bandwidth NAND stacks connected beside an accelerator. The patent explores a more deeply integrated structure in which the processor is placed above a CBA NAND tile while HBM shares the interposer.

These directions can coexist. Standardized HBF may provide a modular path with lower ecosystem risk and easier supplier interchangeability. Directly bonded processor-on-NAND packages may offer shorter connections and tighter optimization at the cost of greater design, thermal, yield, and qualification complexity.

The patent may represent a longer-term extension of the same strategic thesis: flash must move closer to compute. The evolutionary sequence could begin with external SSDs, progress to interposer-connected HBF stacks, and eventually reach vertically bonded NAND-and-compute structures. Different product categories may stop at different points along that path.

A hyperscale inference accelerator could justify full vertical integration because enormous deployment volume spreads development costs. A merchant accelerator sold across many markets may prefer standardized side-by-side HBF. Edge systems might adopt a smaller bonded NAND tile to reduce board space. Sandisk can use its intellectual property across several forms rather than betting on one package.

Most importantly, both HBF and the patented architecture depend on software capable of hiding NAND’s physical latency. Packaging can shorten wires and increase parallelism, but it cannot make a flash cell behave like a DRAM cell.

08 · Performance Analysis

Where the Architecture Could Improve AI Performance

The architecture offers several potential performance advantages, beginning with reduced data-travel distance. Moving model weights from an SSD through PCIe, host memory, and accelerator memory consumes time and bandwidth at multiple stages. Bringing NAND into the package removes or shortens much of that route.

Direct processor-to-memory connectivity can expose more NAND channels simultaneously. An SSD controller aggregates internal flash parallelism but presents it through a relatively narrow standardized interface. A bonded logic tile can provide a custom, much wider path designed specifically for tensor streams.

Persistence could also improve model-loading performance. A package may retain weights between sessions instead of repeatedly copying them from external storage. This could reduce cold-start time, accelerate failure recovery, and allow cloud providers to switch workloads more efficiently. Practical systems would still need integrity validation and security checks.

Near-data processing creates another opportunity. Decompression, filtering, address translation, and sparse-data selection can occur close to NAND, reducing the number of bytes sent to the compute cores. As data movement often consumes more energy than arithmetic, avoiding unnecessary transfers can be valuable.

However, NAND read latency remains orders of magnitude different from local SRAM and substantially higher than DRAM. Physical proximity reduces interconnect delay but does not eliminate cell-sensing time, error correction, or controller scheduling. A dependent request that cannot be predicted may still stall the processor.

The architecture therefore favors throughput over immediate response. Multiple requests must be active so flash operations overlap. Compilers should know future tensor needs. Controllers need deep queues, intelligent scheduling, and large buffers. HBM must capture irregular requests and hot data.

Performance claims should be tested with real models rather than synthetic bandwidth alone. Relevant metrics include sustained tokens per second, time to first token, inter-token latency, tail latency, batch-size sensitivity, model-switching time, HBM cache hit rate, and performance under simultaneous NAND reads and writes.

The design may perform exceptionally well for large, predictable streams while offering little advantage for random, small, latency-dependent access. The system’s success will depend on whether real AI workloads expose enough regularity to keep the pipeline full.

09 · Model Scaling

Turning Storage Density into Near-Compute Capacity

NAND’s density gives the patented architecture its strongest strategic advantage. Modern three-dimensional NAND contains hundreds of vertically fabricated layers and can store far more information in a given footprint than DRAM. This allows a processor package to hold a much larger model pool than an all-HBM design of similar area and cost.

Greater capacity can change accelerator provisioning. When a model requires several GPUs only because it exceeds the memory of one device, adding NAND beneath the processor could reduce the number of accelerators. The system may avoid tensor transfers between GPUs and use expensive compute units more effectively.

Mixture-of-experts models are an especially interesting example. Such models contain many experts but activate only a subset for each token. Storing every expert in HBM is expensive, yet loading experts from remote SSDs may be too slow. Bonded NAND can hold the full expert library, while HBM retains popular or predicted experts.

Multi-model serving presents a similar opportunity. A cloud server may support different language, vision, speech, embedding, and customer-specific models. A large persistent package-level NAND tier could keep many models resident and reduce cold starts. The scheduler can promote models into HBM according to traffic.

Recommendation systems use large embedding tables that frequently exceed accelerator memory. Heterogeneous placement could store colder embeddings in NAND and maintain frequently accessed entries in HBM. Retrieval-augmented generation could place vector indexes or document representations close to compute, although random lookup patterns would require careful optimization.

Capacity is not automatically useful capacity. Every stored model must receive adequate bandwidth. A package that adds many terabytes without scaling controllers and data paths may create contention. Designers must balance NAND capacity, channel count, HBM cache size, interposer bandwidth, and processor throughput.

The architecture also competes with algorithmic methods. Quantization, pruning, sparsity, distillation, and low-rank techniques reduce model size. Yet efficiency improvements often enable developers to build even larger systems, so total memory demand may continue rising. Heterogeneous hardware and model compression are likely to develop together rather than cancel each other.

10 · Business Case

The Economic Promise Goes Beyond Cheaper Bits

NAND normally costs much less per bit than DRAM. HBM adds further premiums for vertical stacking, through-silicon vias, testing, advanced packaging, and constrained supply. Replacing part of an all-HBM capacity requirement with NAND therefore appears economically attractive.

The patented package will not use NAND at ordinary SSD prices. CBA wafers, hybrid bonding, custom logic, advanced interposers, high-speed interfaces, controller development, thermal engineering, and qualification all add expense. Early production may have low yields and limited volume. The relevant comparison is premium near-compute NAND versus premium HBM—not retail SSD capacity versus HBM.

Even so, system-level savings could be substantial. Fewer accelerators may be needed to host a model. Reduced accelerator count also lowers spending on interconnects, switches, host CPUs, server boards, power supplies, cooling, rack space, and maintenance. A larger resident model pool can improve utilization and reduce time lost to model loading.

Persistence may add operational value. A cloud provider can potentially restart an inference service without transferring hundreds of gigabytes from external storage. Model deployments can be staged in advance. Failed workloads may recover more quickly. These benefits affect service availability as well as cost.

There are offsetting expenses. Software teams must optimize placement and prefetching. Operators need flash-health monitoring, encryption, firmware management, and secure sanitization. A tightly integrated package may be expensive to replace if the NAND portion wears out or fails before the processor.

Vendor lock-in is another consideration. A proprietary package can create strong performance but limit second sourcing. Open HBF standards may offer better procurement flexibility than a vertically integrated patented design. Hyperscalers may accept custom solutions because they control both workload and hardware volume; smaller buyers usually prefer standardized components.

The final economic test is not cost per gigabyte. It is cost per useful token, image, prediction, or recommendation at a defined quality and latency target. A lower-priced memory system loses if the accelerator remains idle. A premium package can win if it consolidates servers and increases utilization.

• Measure package cost: processor, HBM, CBA NAND, interposer, controller logic, assembly, and yield.
• Measure fleet impact: accelerator count, networking, rack density, model-loading time, and utilization.
• Measure service quality: throughput, first-token latency, tail latency, uptime, and concurrent users.
• Measure lifecycle cost: endurance, repairability, software development, security, and upgrade risk.

11 · Engineering Challenge

Power Delivery and Heat May Be the Hardest Problems

Placing NAND beneath an AI processor minimizes distance but creates a demanding thermal arrangement. Leading accelerators can consume hundreds of watts and generate substantial heat. NAND performance, retention, and endurance are temperature-sensitive. A memory tile directly below the processor occupies the path through which heat might otherwise leave the compute die.

Three-dimensional integration increases power density. Even if NAND uses relatively little standby power, high-bandwidth operation activates many channels and planes simultaneously. The CMOS logic performs error correction, buffering, scheduling, and interface operations. HBM stacks on the same interposer add further heat.

Designers must create a thermal path that removes heat from the processor without exposing flash to damaging temperatures. Potential techniques include thermal vias, backside power delivery, heat spreaders, microfluidic cooling, optimized floor planning, low-power logic, and workload-aware throttling. Each solution affects cost and manufacturing.

Temperature gradients can cause mechanical stress between materials with different expansion characteristics. Repeated heating and cooling may affect bonded interfaces, micro-bumps, interposers, and package substrates. Reliability testing must model years of data-center operation rather than brief laboratory demonstrations.

Power delivery is equally difficult. The compute die, NAND logic, and HBM require different voltage domains and transient responses. Accelerators can change power consumption rapidly during execution. Stable delivery through a large, complex package demands careful placement of power networks and decoupling components.

The architecture can still reduce system energy. Shorter data paths consume less power than moving model weights through SSDs, host memory, and network links. Fewer accelerators can save considerable rack-level power. NAND also retains data without DRAM refresh.

These potential savings must be measured at the application level. Buyers need energy per token, not just watts per package. A package consuming more instantaneous power may still be efficient if it replaces several servers; conversely, a low-power memory tier can waste energy if it leaves the processor waiting.

12 · Production Risk

Advanced Packaging Could Enable—or Delay—the Concept

The proposed package combines several difficult manufacturing steps. High-layer-count NAND must be fabricated with strong yields. Its array and CMOS wafers must be bonded. The processor must be aligned and bonded to the memory tile. HBM stacks must be assembled. All components must then be integrated through an interposer and qualified as one system.

Yield multiplication creates risk. If every major component has a strong but imperfect yield, the percentage of complete good packages can decline. A defect in low-cost NAND could theoretically cause the loss of an expensive processor and HBM assembly. Known-good-die testing, redundancy, repair mechanisms, and modular assembly sequences are essential.

NAND naturally contains bad blocks and uses controller management to hide them. A near-compute package needs similar resilience without unpredictable performance. The system should continue operating when individual channels, planes, or blocks degrade. Capacity can be overprovisioned, but extra flash consumes area and cost.

Stacking a processor over NAND complicates testing. Engineers need visibility into both components before and after bonding. High-speed interfaces must be tested without adding excessive package pins or expensive equipment time. Firmware and built-in self-test functions become important.

Repairability may be limited. Conventional SSDs can be replaced independently of GPUs. A vertically integrated package combines their lifecycles. If the processor remains useful for six years but the flash wears out earlier, the operator may need to replace the entire module. Designers can mitigate this with read-heavy workload policies, generous endurance margins, spare capacity, and modular package options.

Advanced packaging capacity is already constrained by demand for HBM accelerators. Sandisk’s design could reduce the amount of HBM needed per unit of model capacity, but it may increase demand for hybrid bonding, large interposers, and complex assembly. The architecture shifts packaging requirements rather than eliminating them.

A commercially successful product must achieve sufficient yield to preserve NAND’s cost advantage. If packaging expense overwhelms media savings, standardized side-by-side HBF or CXL-attached memory may offer a better balance.

13 · Software Stack

Hardware Integration Is Only Half the Invention

A processor, HBM, and NAND can share a package, but they will not behave as one efficient memory system without sophisticated software. The runtime must understand which data belongs in each tier, when movement should occur, and how to hide delays behind computation.

Compilers have an important advantage: AI model graphs are often predictable. The compiler knows layer order, tensor dimensions, dependencies, precision, and reuse patterns. It can arrange weights across NAND channels, align transfers with page boundaries, schedule prefetch operations, and reserve HBM for hot tensors.

Runtime behavior is less predictable. Request volume changes, context lengths vary, and mixture-of-experts routing depends on input. The runtime must monitor access patterns and adapt placement. Popular experts may be promoted to HBM, while cold experts remain in NAND. Several models may compete for the same fast-memory capacity.

The system needs a programming model. HBM and NAND could appear as separate address spaces, a unified virtual memory space, a managed tensor store, or a transparent cache hierarchy. Each option involves trade-offs. Explicit APIs provide control but increase developer effort. Transparent migration simplifies applications but can cause unexpected stalls.

Page size is particularly important. Operating-system pages may not match the structure of AI tensors or NAND transfer units. A tensor-aware runtime can move complete layers, experts, attention blocks, or embedding shards. Managing meaningful AI objects may produce better performance than generic paging.

Prefetch accuracy determines whether NAND latency is visible. Reading too late stalls computation. Reading too early occupies HBM and can evict useful data. Reading an expert that is never selected wastes bandwidth and power. Prediction algorithms must balance these costs.

Observability is also essential. Operators need telemetry for HBM hit rates, NAND bandwidth, queue depth, tail latency, corrected errors, temperature, wear, model residency, and data-movement volume. Cloud schedulers must know which servers are suitable for each model and latency target.

Software compatibility will affect adoption speed. Ideally, popular frameworks and serving engines should use the architecture without requiring model developers to rewrite applications. Advanced users should retain explicit controls for specialized deployments. HBM has a major advantage today because its ecosystem is established; Sandisk’s concept must earn equivalent support.

14 · Enterprise Readiness

Endurance, Data Integrity, and Persistent Security

NAND flash tolerates a finite number of program-and-erase cycles. AI inference weights are generally read-mostly, making them a favorable workload. Yet production systems still update models, rotate tenants, write metadata, modify caches, and recover from errors. Uncontrolled writes could reduce package lifetime.

The controller must consolidate writes, perform wear leveling, maintain spare blocks, and prevent hot metadata locations from wearing prematurely. HBM or SRAM buffers can absorb temporary writes and commit them to NAND in larger batches. Software can classify data and prohibit unsuitable write-intensive workloads.

Error correction is unavoidable because NAND density depends on storing information in cells whose electrical margins can vary with wear, temperature, and time. Strong error-correcting codes preserve integrity but consume logic, latency, bandwidth, and power. End-to-end checksums should verify that model weights remain correct from storage through computation.

Persistence creates a new security model. HBM is volatile; NAND may retain proprietary weights after shutdown or reassignment. A cloud provider must ensure that one tenant cannot recover another tenant’s models. Encryption should be built into the memory tile, with keys controlled by trusted hardware and destroyed during sanitization.

Secure boot and attestation are also necessary. The processor needs confidence that controller firmware has not been altered and that the model stored in NAND is authentic. Firmware updates must be signed, rollback-protected, and recoverable. These requirements make the NAND logic tile part of the trusted computing base.

Failure isolation will determine serviceability. A degraded NAND channel should reduce capacity gracefully rather than disable the complete accelerator. HBM errors, processor faults, and interposer failures need separate diagnosis. Telemetry must identify whether a slowdown originates in software placement, thermal throttling, media wear, or physical connectivity.

Enterprise buyers will require defined endurance, retention, uncorrectable error rates, warranty conditions, secure-erasure procedures, firmware support, and expected useful life. The package cannot rely on vague assumptions that read-heavy AI is automatically safe for flash.

15 · Deployment Opportunities

Which Workloads Could Benefit First?

The first successful deployments will likely be controlled systems in which one vendor optimizes the model, compiler, runtime, controller, and package together. High-throughput inference is a better starting point than general-purpose acceleration because it offers predictable access and a high ratio of reads to writes.

Ultra-low-latency services may still prefer all-HBM systems. Very small batches provide fewer opportunities to hide NAND latency. Dynamic workloads with irregular expert routing or frequently changing data may require larger HBM caches. The architecture should therefore be offered as a configurable platform rather than one universal ratio of flash to DRAM.

16 · Industry Impact

A New Competitive Field for Memory and Packaging Suppliers

AI infrastructure has increased the strategic importance of HBM, advanced logic, foundry capacity, and packaging. Sandisk’s patent could add high-performance NAND to that group. Instead of serving merely as distant storage, flash becomes an architectural component of the accelerator itself.

For NAND suppliers, near-compute memory offers a premium market beyond commodity SSDs and consumer storage. It demands high-quality media, specialized logic, hybrid bonding, advanced controllers, and deep customer collaboration. Suppliers able to combine these capabilities may achieve greater differentiation and more stable margins.

For HBM manufacturers, the concept is not purely threatening. Every heterogeneous package may still require HBM. A broader market for affordable inference accelerators can increase total memory demand. Companies with both DRAM and NAND expertise are well positioned to supply complete tiered solutions.

Foundries and packaging providers could gain new business from logic tiles, interposers, hybrid bonding, and multi-die assembly. Equipment makers may see demand for wafer bonding, thinning, inspection, testing, and thermal-compression systems. Substrate and materials suppliers will need solutions for larger, denser packages.

Accelerator vendors retain considerable power. They control memory controllers, software ecosystems, package design, and access to leading compute customers. Sandisk will likely need partnerships, licensing, or co-development arrangements. A memory architecture cannot succeed at scale without processor support.

Hyperscalers may develop custom versions because they can optimize hardware around known model-serving workloads. Their purchasing volume justifies specialized silicon and packaging. Merchant products must support a wider range of applications and may favor the more standardized HBF approach.

The architecture also competes with CXL memory, larger HBM4 configurations, direct SSD access, LPDDR-based inference systems, and software-based model compression. Its advantage must be large enough to justify a more integrated and potentially less serviceable package.

17 · Roadmap

What Must Happen Before the Patent Becomes a Product?

Observers should distinguish patent activity from each commercialization stage. A granted patent confirms legal protection, not technical readiness. A laboratory package confirms feasibility, not yield. A customer evaluation confirms interest, not volume. A design win confirms integration, not economic success.

Standard HBF may reach practical adoption before a fully bonded processor-on-NAND package because it requires less radical integration. The patented design could then emerge as a premium or second-generation option after controllers and software have matured. Alternatively, parts of the invention may appear gradually in other products without one exact commercial implementation matching the patent diagrams.

18 · Final Verdict

This Is a Blueprint for Heterogeneous AI Memory—not the End of HBM

Sandisk’s patent deserves attention because it attacks AI’s memory problem at the package-architecture level. It does not merely make an SSD faster or add another memory stack. It proposes placing high-capacity non-volatile memory directly beneath compute while retaining HBM on the same interposer.

The design recognizes an important reality: no single memory technology optimizes latency, bandwidth, capacity, persistence, endurance, power, and cost. HBM excels at urgent and frequently changing data. NAND excels at dense, economical, persistent capacity. Combining both near the processor can produce a more efficient system than forcing either medium to perform every role.

The patent also illustrates the convergence of storage and memory. NAND remains physically flash, but package proximity, wide interconnects, controller intelligence, and tensor-aware software can make it operate as part of an accelerator’s memory hierarchy. The distinction between “memory” and “storage” becomes an architectural policy rather than simply a physical location.

Nevertheless, the concept faces major obstacles. NAND latency cannot be eliminated. Flash endurance and security require careful management. Processor-on-NAND stacking creates serious thermal and yield risks. Advanced packaging is expensive, and software must predict data movement accurately. A patent provides no evidence that all of these challenges have been solved.

The architecture is most credible for read-heavy AI inference, mixture-of-experts models, large embedding systems, and multi-model hosting. HBM will continue to dominate frontier training and low-latency working memory. Conventional SSDs will remain valuable for cold storage and datasets.

Bottom line: Sandisk is not removing HBM from the AI accelerator. It is putting HBM in the role where its premium delivers the greatest value and moving NAND close enough to absorb the capacity burden. If production engineering validates that strategy, the processor-on-NAND package could become an important model for the next generation of inference hardware.

19 · Buyer Checklist

Questions Infrastructure Buyers Should Ask

• Architecture: Is NAND directly bonded beneath compute, connected as an HBF stack, or attached through a conventional storage interface?
• Workload: What percentage of memory traffic consists of predictable reads, random reads, and writes?
• Performance: What are sustained throughput, first-token latency, tail latency, and small-batch performance?
• Tiering: How much HBM is included, and which data structures remain permanently in the hot tier?
• Power: What is total package power and energy per token under sustained operation?
• Thermals: How does the design protect NAND retention and endurance beneath a high-power processor?
• Reliability: Can degraded NAND capacity be isolated without replacing the full accelerator package?
• Security: How are persistent model weights encrypted, attested, and securely erased?
• Economics: Does the architecture lower cost per token after software, packaging, yield, power, and service life are included?

Frequently Asked Questions

Five FAQs About Sandisk’s Processor-on-NAND Patent