BMS Battery Management System: Definition, Key Functions, Diagrams, LiFePO4 Notes, and Cross-Brand IC Choices

What is a Battery Management System (BMS)?

A Battery Management System (BMS) is the electronics that monitor cell and pack voltage, current, and temperature; estimate state of charge and health; balance cells; enforce safety limits; and command charge, discharge, and contactors. It reports diagnostics over CAN/LIN, safeguarding safety, performance, reliability, and service life across EV, ESS, portable, and industrial battery packs in varied operating environments and climates.

On this page: block/circuit diagrams (PDF), LiFePO4 notes, 12V/24V/3S cases, cross-brand IC choices, and price factors.

Key Functions of a Battery Management System (BMS)

The core function of a BMS (Battery Management System) in electric vehicles is to coordinate five roles that together govern safety and performance: Monitoring, Protection, Balancing, Thermal management, and Reporting & Communication.

Together these functions drive safety, performance, longevity, and reliability—see why they matter next.

Why is a BMS Important?

In practice, why is a BMS important? Because it turns raw cell measurements and control logic into four outcomes that decide whether a battery pack is safe, usable, and predictable across EV, ESS, portable, and industrial duty cycles.

How these outcomes are prioritized depends on the use case—see where BMSs are used and how those priorities drive topology choices (centralized, distributed, modular).

Where Are BMSs Used?

In practice, where are BMS used? Across four major contexts—EV, ESS, portable, and industrial—each with distinct priorities that shape topology, wiring, and communication choices.

Different priorities across these domains drive different topology choices (centralized, distributed, modular) and wiring complexity—next, we compare them.

BMS Topologies & System Forms

Before drawing a battery management system block diagram, choose the system topology. Centralized, distributed, and modular forms trade wiring complexity, redundancy, diagnostic coverage, scalability, EMC risk, and service strategy—those choices anchor the electrical blocks you will place next.

Once the topology is set, the battery management system block diagram falls into place—measurement, balancing, contactors/precharge, isolation, comms, and thermal blocks. Next: see the Block & Circuit Diagrams (with PDF) and how each function maps to hardware.

See also: application contexts (EV/ESS/Portable/Industrial) and LiFePO4 notes for chemistry-specific considerations.

BMS Block Diagram & Circuit Diagram

This section provides a bms battery management system block diagram and a bms battery management system circuit diagram, plus a combined PDF, to anchor how five key functions map onto concrete hardware blocks and connections.

Monitoring: Sensing Chain & Estimation

Monitoring anchors every protection decision. Voltage, current, and temperature must be measured with known accuracy, latency, and integrity—otherwise SOC/SOH estimates drift and protection either trips late or too often.

From Cell Taps to Host: the Sensing Chain

• Voltage: cell taps → AFE/ADC (with open-wire detect) → synchronized sampling (isoSPI/daisy chain) → MCU.
• Current: shunt+amp (high/low side) or Hall/fluxgate → isolation/conditioning → ADC.
• Temperature: NTC/RTD placement per string/module → filtering and plausibility checks.
• Timestamps & alignment: keep samples coherent; aliasing and latency budgets shape downstream debouncing and lockouts.

Voltage Sampling Architectures

Choose an architecture that matches series count, harness length, EMC context, and service model. Each has distinct pros and trade-offs.

Current Sensing Choices

• Shunt + amplifier: best linearity and bandwidth; watch loss/thermal design, offset/drift, and Kelvin routing.
• Hall effect: galvanic isolation and low insertion loss; manage offset/temp drift and external field sensitivity.
• Fluxgate: high accuracy and low drift for DC; more complex and costly; footprint and supply considerations.
• Shared inverter/bus sensing: convenient but noisy; synchronize sampling and model the bandwidth limits.

Temperature Sensing & Placement

• NTCs per string/module with good thermal coupling; avoid air gaps and slow response paths.
• Cover hot spots (high-R paths, power devices) and cold-charge risks; verify with drive/charge profiles.
• Plausibility checks: open/short detection, cross-sensor consistency, and rate-of-change sanity.

Synchronization, Latency & Data Integrity

• Align time bases across AFE chain; use simultaneous sampling where available to avoid aliasing between cells.
• Budget end-to-end latency (sense → decide → act); it sets debounce and lockout timing in protection.
• CRC, frame counters, watchdogs, and open-wire tests ensure data trustworthiness before decisions.

SOC & SOH Estimation

• Coulomb counting: excellent dynamics but drifts—periodically re-anchor with OCV windows.
• OCV–SOC curves: temperature-dependent; require rest to be accurate; blend with current history.
• Fusion: EKF/UKF/impedance-tracking blends voltage, current, and temperature to stabilize SOC and infer SOH (capacity & resistance).
• Define recalibration triggers (full charge, rest periods, temp gates) and track estimation uncertainty.

Protection logic consumes these measurements and estimates. Next, see how thresholds, debounce, lockouts, and contactor/precharge control implement safety policies in Protection.

Protection: From Thresholds to Actions

Protection consumes the measurements from Monitoring and turns them into decisions and actions. Policies combine a threshold window with debounce and hysteresis; severe events latch into a lockout state until a verified recovery path is followed.

Threshold Models (V/I/T)

• Voltage windows: cell/pack UV/OV with temperature- and SOC-aware limits; hysteresis to avoid chatter.
• Current limits: charge/discharge limits plus fast SCP comparators (hardware path) and I²t/time curves (software path).
• Temperature gates: high-temp shutdowns and low-temp charge inhibition; sensor open/short/offset fall back to conservative derates.
• Rate triggers: dV/dt, dI/dt, dT/dt to catch runaways before absolute limits are crossed.

Decision & Severity

• Levels: Advisory → Limited (Derated) → Trip (Latched), each with distinct timers and user feedback.
• Aggregation: persistence counters, multi-sensor consensus, and plausibility checks to resist noise and single-point errors.
• Recovery: auto-retry after cooling/voltage return, or manual reset for latched hazards; keep logs for traceability.

Actuation & Sequencing

• Contactors & precharge: sequence precharge, validate ΔV convergence and timeout; on failure, open to a safe state.
• eFuse/SmartFET: fast current limiting or disconnect; thermal reset vs latched trip behavior as policy.
• Post-trip checks: bleed residual energy, verify for weld detection, coordinate with insulation monitoring.
• Fail-safe: define safe states (charge-only / discharge-only / open) and entrance conditions.

Condition → Action Matrix

Balancing must respect protection windows and thermal budgets, while thermal control can elevate or relax power limits. Next, see Balancing and Thermal management to understand those interactions.

Balancing: Passive, Active, and When to Enable

Balancing reduces cell divergence so usable capacity is not capped by the weakest cell. Strategies must respect protection windows and thermal budgets; otherwise the remedy adds heat and accelerates aging instead of improving range or runtime.

Mechanisms

Passive vs Active vs Hybrid

When to Balance (and When Not To)

• Prefer at rest / near end-of-charge: voltage better represents SOC; results persist after use.
• Suspend near protection limits: close to UV/OV or during faults/lockouts from Protection.
• Thermal gates: enforce per-cell temperature and pack thermal budget; pause on excessive rise.
• Sensor plausibility first: if V/T readings are suspect (open/short/drift), delay balancing until cleared.
• Precharge/contactors switching: pause during transients to avoid misinterpretation of ΔV.

Triggers, Targets, and Stop Criteria

• Triggers: ΔV@rest and/or ΔSOC beyond target; IR spread indicating divergence; time-since-last-balance.
• Targets: policy-defined ΔV/ΔSOC bands rather than fixed numbers; prioritize largest outliers first.
• Stop: when ΔV@rest/ΔSOC falls below target, daily energy budget is consumed, or thermal rise exceeds limits.

Scheduling & Budgets

• Set bleed/transfer current limits and a daily/weekly energy budget; record per-cell cumulative balanced energy.
• Use fair scheduling: largest-error-first, rotate between clusters, and avoid concentrating heat on one area.
• Coordinate with charger/EMS to exploit long dwell periods (e.g., overnight for ESS or parked EVs).

Thermal & Life Impact

• Balancing is a heat source; integrate with Thermal management to cap temperature rise.
• Over-aggressive balancing can increase cycle aging; seek diminishing-returns point where SOH benefits plateau.
• Log temperature during balancing to correlate hot spots with SOH drift over time.

Diagnostics & Recordkeeping

• Keep a history of per-cell ΔV@rest, ΔSOC, IR estimates, and balanced energy.
• Flag persistent outliers for service; correlate with protection events and thermal excursions.

Balancing heat and scheduling tie directly into thermal policy and power limits. Next, see Thermal management for gates that govern charging, derating, and safe operation.

Thermal Management: Cooling, Heating, and Low-Temperature Charge Gates

Thermal management turns temperature readings into charge/discharge gates and power limits, then drives fans, pumps, valves, and heaters with hysteresis and safety margins. Policies protect safety, slow SOH drift, and coordinate with charging so availability never outruns cell integrity.

Sensing & Estimation

• NTCs per cell-string/module plus cold-plate inlet/outlet and enclosure sensors; verify plausibility and detect opens/shorts.
• Estimate core temperature with a simple RC model and track ΔT between hot spots and bulk to avoid hidden thermal soak.
• Use drive/charge profiles as feedforward to schedule cooling or preconditioning ahead of demand.

Cooling Strategy

• Control fans, pumps, and valves via bang-bang+hysteresis, stepped bands, or PID with feedforward; prioritize hot zones.
• Define a thermal budget and ramp limits to avoid oscillation; coordinate with balancing heat and reduce balance current if needed.
• For liquid/coolant loops, monitor pressure/flow and degrade gracefully on sensor faults.

Heating & Preconditioning

• Apply PTC pads, resistive heaters, or refrigerant reverse-cycle; insulate appropriately for efficient warm-up.
• Precondition before expected charging: EVs can use route/charger info; ESS can use tariff/Load windows.
• Honor insulation and safety limits; heating and contactor policies from Protection must not conflict.

Low-Temperature Charge Limits

• Gate charging by temperature windows: inhibit first, then allow limited charge only after preconditioning or natural warm-up.
• Make gates chemistry-aware—see LiFePO4 notes—but express them as policy bands rather than hard numbers.
• Expose gate state to the host (inhibited/derated/normal) so chargers and users see predictable behavior.

Power Limits & Derating

• Set discharge/charge power limits from temperature trajectory and ΔT; treat short spikes and sustained soak differently.
• Use derating to remain usable near limits; reserve lockout for hazards per Protection.
• Coordinate with charger/EMS to advertise limits early (CAN/LIN/ethernet), smoothing user experience.

Thermal Levers → Outcomes

Operating States → Thermal Policy

The current thermal state and gate/derate flags should be exposed to the host and logged for analysis. Next, see Reporting & Communication for diagnostics and interfaces.

Reporting & Communication (CAN/LIN/isoSPI & Diagnostics)

BMS reporting exposes state, limits, and events, while communication layers carry them to hosts. Internally, isoSPI ties the AFE chain to the MCU; externally, isolated CAN/LIN/RS-485/Ethernet link the pack to an ECU, EMS, charger, or fleet server.

Real-time Signals

• Pack: V_pack, I_pack, SOC, SOH, P_chg/P_dis limits, thermal gate (inhibit/derate/normal), ΔT, T_max/T_min.
• Cell: V_min/V_max and IDs, imbalance metrics (ΔV@rest/ΔSOC), balancing state and budget.
• Health: contactor states, precharge status, insulation monitor result, link health (CRC, drop counters), watchdog status.
• Timing: message periods, counters, timestamps; loss-of-comms fallback and degraded modes.

Diagnostics & Logging

• Fault codes mapped to UDS/J1939/CANopen/Modbus as needed; keep a human-readable table in manuals.
• Freeze-frame per event: time, cell min/max, pack I/V/T, state/limits, counters, link health.
• Lifecycle stats: high-temp dwell, low-temp charge attempts, contactor cycles, cumulative balanced energy.

Interfaces & Protocols

• isoSPI: intra-module daisy chain with CRC and open-wire checks; high CMRR, short distance.
• CAN/CAN-FD: EV/industrial backbone; common app layers: UDS, J1939, CANopen.
• LIN: simple peripherals/HMI with low bandwidth.
• RS-485/Modbus: ESS cabinets and arrays; long distance, simple polling.
• Ethernet: high-bandwidth telemetry, service, and secure management links.

OTA, Calibration & Safety

• Bootloader with A/B images, signed updates, rollback protection, and power-safe commit.
• Calibration delivery for threshold windows and policy tables; audit changes and require versioned approvals.
• Access control and rate limits to prevent bus flooding and unauthorized writes.

Who Decides What?

• BMS: declares safe availability—SOC/SOH, thermal gates, power limits, and trips.
• ECU/EMS: plans torque/charge profiles and user experience based on BMS limits.
• Charger: follows BMS gates/limits; reports faults back over the chosen protocol.

Reporting fields and limits are chemistry- and series-count-aware—see LiFePO4 notes and 12V/24V/3S cases for how policies adapt across chemistries and pack sizes.

Chemistry: LiFePO4 (LFP) vs NMC/NCA

Chemistry shifts OCV shape, temperature sensitivity, charge acceptance, and safety posture—so BMS windows, low-temperature gates, and balancing triggers must adapt. This section targets bms battery management system lifepo4 intent and contrasts LFP with NMC/NCA using engineering policies (no hard numbers).

SOC/SOH Estimation Differences

• LFP: flatter OCV→SOC slope; rely more on coulomb counting + temperature compensation + history fusion (EKF/impedance tracking). Track estimation uncertainty and re-anchor during rest.
• NMC/NCA: steeper OCV slope makes rest-OCV windows more informative; still blend with current/temperature history. SOH uses capacity and resistance together.

Charging Strategy & Low-Temperature Gates

• LFP: prioritize cell integrity—gate as inhibit → precondition (heat) → derate → normal. Near end-of-charge, use current/time + thermal policy since dV/dt is modest.
• NMC/NCA: window can be wider but thermal risk is higher—strong cooling and ramped power limits. Use gates as policy bands rather than fixed thresholds.
• Expose gate state to host (inhibited/derated/normal) for predictable charger behavior; see Reporting & Communication.

Balancing Triggers & Method

• LFP: trigger at rest or near end-of-charge where voltage reflects SOC; prefer passive or hybrid with thermal-aware current limits and overnight windows (ESS/parked EV).
• NMC/NCA: earlier detection from voltage sensitivity; for large packs, active or hybrid balancing accelerates convergence.
• All balancing respects protection windows and thermal budgets; see Protection and Thermal.

Protection Windows & Derating Style

• LFP style: conservative low-temperature charge gates, cautious end-of-charge policy; emphasize threshold window, debounce, hysteresis with preconditioning before allowing charge.
• NMC/NCA style: emphasize thermal headroom and cooling authority; use derating to preserve predictability near limits and reserve lockout for hazards.

Reporting & Diagnostics (Chemistry-Aware)

• Report Chemistry ID, charge gate state, preconditioning state, estimation uncertainty (especially for LFP), and current power limits.
• Log high-temp dwell, low-temp charge attempts, cumulative balanced energy, and correlate with SOH drift over time; see Reporting & Communication.

Chemistry choices flow into common “named voltages” and series counts used in products. Next, see 12V/24V/3S cases for how policies and topology scale across typical pack sizes.

12V / 24V / 3S Cases (DIY & Entry-Level)

This section addresses 12v bms, 24v bms, and 3s bms use cases for beginners and DIYers—mapping “named voltages” to series counts by chemistry, clarifying discharge current levels, balancing needs, and common traps.

Discharge Current Levels (C-Rate Tiers)

• Low tier: light loads, continuous current well within wiring/connector limits; prioritize efficiency and small passive balancing.
• Mid tier: intermittent peaks; distinguish continuous vs burst ratings and coordinate with thermal budget and enclosure airflow.
• High tier: tools/UAV/inverters; specify fast protection paths (eFuse/SmartFET + I²t), robust precharge, and verify terminal temperature under peak duty.

Balancing Needs

• Small packs with good matching: passive bleed at rest/EOC is usually sufficient.
• Higher energy or uneven temps: consider active or hybrid to shorten convergence and reduce wasted heat.
• Do not balance near UV/OV, during faults/lockouts (Protection), or when temperature gates are binding (Thermal).

Quick Scenario Reference

DIY Selection Checklist

Before selecting a 12V, 24V, or 3S BMS, it is also useful to estimate the expected runtime of your battery pack under real load conditions. You can use this battery life calculator to quickly compare battery capacity, load current, voltage, and estimated operating time before finalizing the BMS current rating and pack configuration.

• Series match: confirm 3S/4S/6S/8S matches chemistry and “named voltage.”
• Current rating: separate continuous vs peak; verify wiring, terminals, and heat dissipation.
• Balancing: none / passive / active—choose based on pack size and dwell time.
• Communication: none / SMBus-I²C / CAN-LIN—pick what your charger/host speaks.
• Thermals & install: number/placement of temp probes; airflow or heatsink provisions.
• Protection features: SCP fast path, precharge availability, eFuse/SmartFET vs mechanical relay.

Common Pitfalls

• Treating the BMS as a charger: the BMS limits or disconnects; the charger defines the charge curve.
• Equating 3S with 12V LFP: chemistry and series differ—do not cross-apply thresholds or chargers.
• Only reading “A” on the label: ignore continuous vs peak, wiring gauge, connector ratings, and thermal rise at your peril.
• Mixing cells: brand/age mismatch confuses estimation and makes balancing ineffective.
• Skipping precharge: hard-connecting capacitive loads leads to sparks, welds, and EMI issues.
• Cold charging anyway: respect low-temperature charge gates (see Thermal and LFP notes).

Series count and current tier drive AFE channels, switch ratings, isolation, and bus choices. Next: select chips and devices across brands in Cross-brand IC Choices.

Cross-brand IC Choices (Function-Block Selection Matrix)

To beat single-brand brochures, choose parts by function block → constraints → topology rather than logos. This section aligns with battery management system bms intent and maps five blocks—Monitor/AFE, Balancer, SmartFET/eFuse, Isolation, MCU—onto real engineering trade-offs and interchangeable routes.

Selection Playbooks (by Function Block)

Monitor / AFE

• Match channel count & daisy-chain capability to series count and harness length.
• Require open-wire detect, synchronized sampling, and end-to-end CRC for chain integrity.
• Budget input RC/ESD protection so it doesn’t corrupt dynamics or accuracy.
• Decide on integrated passive-bleed vs external drivers early (thermal ownership).
• Plan chain-break handling, addressing, and re-enumeration procedures.

Balancer (Passive / Active / Hybrid)

• Passive: validate bleed power and hotspot layout; enforce thermal budgets.
• Active: choose inductor/capacitor architecture; verify efficiency and EMI mitigation.
• Expose policy hooks (ΔV/ΔSOC thresholds, per-cell limits) to firmware.
• Coordinate with charger/EMS to exploit long dwell windows.

SmartFET / eFuse

• Size by continuous current and burst duty; check SOA and copper thickness.
• Use fast SCP paths (comparator or device internal) plus I²t software path.
• Confirm reverse-battery, short-to-ground/battery, and over-temp behaviors.
• Define latched vs self-recovery per protection policy (see Protection).

Isolation

• Choose isolators by CMTI, working voltage, creepage, and temperature grade.
• For CAN/LIN, prefer integrated isolated transceivers to simplify EMC.
• Co-design isolated DC/DC placement, return paths, and surge/ESD strategy.

MCU

• Ensure native CAN-FD/LIN/Ethernet as needed; don’t rely on bit-banged workarounds.
• Security/OTA: signed images, rollback protection, A/B slots; hardware crypto accelerators help.
• Support SOC/SOH algorithms with ADC timing, DMA, and math accelerators.

Replacement & Verification Plan

• Dual-source per block (Primary/Backup) and keep pin/peripheral escape room on the PCB.
• Bench tests: noise/temperature drift, open-wire/short injection, chain-break behavior, CAN bus loading/arbitration.
• Pre-EMC: near-field scan, dv/dt stress around contactors, isolation CMTI checks.
• Software: uniform DTC/freeze-frame fields across vendors; calibration versioning; OTA power-fail recovery.

With blocks shortlisted, the next question is cost, availability, and substitution risk. Continue to Price & Procurement.

Price Factors & Procurement (No Numbers, Just Drivers)

Total cost for a BMS is the outcome of design constraints and supply realities—not a single part’s sticker. To meet bms battery management system price intent without quoting numbers, this section explains the drivers that shape BOM and sourcing so your RFQs land on-target.

What Drives BMS Cost?

• Series count (cells-in-series): AFE channel count/chain length, open-wire coverage, connector pin-count, harness complexity, isolation boundaries; see Topologies & Monitoring.
• Current / power path tier: eFuse/SmartFET vs contactors, SOA & I²t, precharge network sizing, copper weight/heatsinking, terminal & connector class; see Protection.
• Balancing method: passive vs active vs hybrid, magnetics & EMI control, thermal budget, dwell-time assumptions; see Balancing.
• Interfaces & isolation: isoSPI/CAN-FD/LIN/RS-485/Ethernet mix, isolated transceivers, digital isolators, isolated DC/DCs, creepage/CMTI needs; see Reporting.
• Compliance & certification: UN 38.3, IEC/UL, automotive/industrial qual, test samples and documentation cycles.
• Functional safety & software: ASIL targets, FMEDA/safety manual availability, diagnostics coverage, bootloader/OTA security and signing.
• Environment & mechanics: temperature grade, vibration, enclosure/connector sealing & locking, conformal coating, manufacturing test fixtures.

From Design to Purchase: A Practical Flow

1. Freeze constraints: topology/series/current/buses/safety (S5, S14).
2. Dual-source plan: Primary/Backup per function block; mark non-substitutable items.
3. Create BOM variants: Base / Cost-down / Hi-Rel with swappable grades/footprints noted.
4. RFQ & lead-time check: authorized channels only; capture MOQ/NCNR, alternates, lead-time bands.
5. PPV & validation: EMC/thermal/open-wire/chain-break/OTA tests; record yield & rework.
6. Risk & ramp: VMI/buffer stock, PCN/EOL watch, periodic alternate drills.

Negotiation Levers & Common Risks

What to Include in Your RFQ/BOM

• Design ID & stage (prototype / pilot / mass); EAU forecast.
• Per line: MPN, function block (AFE/Isolation/MCU/… ), qty/board, acceptable alternates, interface/protocol needs.
• Temperature grade, compliance targets (UN38.3/IEC/UL/ASIL), desired lead-time window.
• Attachments: schematic/block diagram PDF, key constraints (series/current, buses, safety goal).

Many readers next ask for “the best BMS” or an open-source design. The right answer depends on constraints and maintenance responsibilities—continue to [S16] Best & Open-Source.

“Best” Evaluation Framework & Open-Source BMS Boundaries

Instead of a one-size list, best means “best fit under your constraints.” This section frames best bms battery management system as a weighted, evidence-based score, and clarifies where an open source bms battery management system fits—and where it does not.

Evaluation Rubric (0–5 with weights)

Score each criterion 0–5 and apply scenario weights. Anything failing a must-have gate is eliminated before scoring.

Weighting Templates (tune to your use case)

• EV: Safety/Protection, Thermal, Interfaces, Compliance carry highest weights; strong bias to diagnostics.
• ESS: Interfaces (RS-485/Ethernet), Supply/Lifecycle, Balancing efficiency, Maintainability/OTA, Compliance.
• Portable: Monitoring accuracy, TCO Fit, Docs/Tooling, small-form thermal & protection simplicity.
• Industrial: Reliability/Diagnostics, Interfaces (CAN/J1939), Supply/Lifecycle, Performance & Derating.

Must-Have Gates (Eliminate before Scoring)

• Missing open-wire/CRC/frame counters on the measurement chain.
• No documented protection state machine (lockout, debounce, precharge, weld-check).
• No thermal gates (low-temp charge inhibit/derate) or undefined derating behavior.
• OTA without signing/rollback or no calibration governance.
• No credible path to UN 38.3 / IEC/UL where required.

Open-Source BMS: Where It Fits (and Doesn’t)

With a shared rubric and boundary conditions set, the last step is to tie everything together and answer common questions. Continue to [S17] Summary & FAQ.

Frequently Asked Questions

Downloads (PDF)

Centralized resources for quick reference and sharing. Each file includes a one-line “What you’ll get” so users and AI can understand scope at a glance.

• bms-block-circuit-diagram.pdf — What you’ll get: a printable Block & Circuit overview that maps Monitoring/Protection/Balancing/Thermal/Communication to specific IC blocks and interfaces for reviews and markup. (See S6)
• bms-ic-selection-cheatsheet.pdf — What you’ll get: a one-page cross-brand IC quick reference (function blocks × topology fit × interfaces × safety documentation) to build Primary/Backup routes fast. (See S14)
• lifepo4-bms-design-notes.pdf — What you’ll get: concise LiFePO4 design notes: low-temperature charge gates, OCV→SOC handling, balancing triggers, and reporting fields (strategy-based, no hard numbers). (See S12)

Need editable sources or BOM formats (CSV/XLSX)? Contact us and we’ll share templates aligned with this guide.