Power Bus Isolators & Protection Helpers

Make telemetry and control rails trustworthy under real-world power events. We isolate PMBus/SMBus/GPIO with high-CMTI behavior, block reverse/backfeed using ideal-diode controllers and back-to-back FETs, and shape bring-up via UVLO/OVLO, dV/dt, and PG/Alert alignment.

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Browse sections

1 Answer Box 2 What is it 3 Working Principle 4 Technical Breakdown 5 Key Metrics 6 Design Guidelines 7 Troubleshooting Matrix 8 Applications & Schematics 9 Reference ICs & CTA 10 Validation & Measurement Plan 11 FAQ

Answer Box (Decision-Ready)

Problems to Solve

Isolation: Provide high-CMTI, fail-safe galvanic isolation for PMBus/SMBus/GPIO/PG/Alert to prevent control/telemetry faults under GPD, surge, and hot-plug.
Protection: Stop reverse polarity and backfeed (“ghost power”) using back-to-back MOSFETs with ideal-diode control.
Controlled Startup: UVLO/OVLO windowing + slew-limited dV/dt + PG/Alert alignment for deterministic bring-up and traceability.

Targeted Solutions

High-CMTI isolation + fail-safe: bidirectional open-drain reconstruction; predictable idle on cold start.
Back-to-back MOSFETs + ideal-diode control: reverse differential shuts off; low forward drop with measurable leakage.
Startup governance: UVLO/OVLO gating, controlled dV/dt, and PG/Alert cadence alignment with timestamps.

Icons: 🧲 Isolation 🛡️ Backfeed ⏱️ Controlled Start

Selection Triplet

CMTI ≥ 50–100 kV/µs with proven I²C Fast-mode Plus (1 MHz) timing margins.
Back-to-back MOSFET R_DS(on) × thermal path passes i²t and SOA checks.
UVLO hysteresis 3–5% + debounce ≥ 1–5 ms; no backfeed on power-down.

CMTI [kV/µs]

≥ 50–100

R_DS(on) [mΩ] per FET

≈ 2–10

UVLO [%] / Debounce [ms]

3–5 / ≥ 1–5

Risk Alerts

Isolation delay + large cold pull-ups → Fm+ timing edge.
Protection not latched off on reverse → thermal shock.
Wrong power-up sequence → stuck bus / false PG.

Hero (3:2): isolation for PMBus/SMBus/GPIO, reverse/backfeed blocking, and UVLO-controlled startup; KPI cards for CMTI, RDS(on), UVLO — Figure 1 — Isolation / Backfeed / Controlled Startup overview (3:2)

What is it ｜ Definition & Boundary

Definition

A device family focused on galvanic isolation, reverse/backfeed protection, and controlled startup for PMBus/SMBus/I²C/GPIO/PG/Alert. It keeps the control/telemetry island usable, trustworthy, and auditable through ground-potential differences, EMC/ESD events, hot-plug, and power ramps.

Objects

Buses: I²C/SMBus/PMBus (SDA/SCL/ALERT).
Alerts/Status: PG, Fault, GPIO.
Power clamping: reverse polarity & backfeed blocking; ideal-diode behavior.
Deterministic startup: UVLO/OVLO windows, controlled dV/dt, PG/Alert alignment.

Scope: interfaces/protection/startup determinism only. It does not cover power-conversion topologies, active decoupling, sequencing, or voting.

When to Use

Multi-board or long interconnects with GPD risks.
High dv/dt surroundings requiring higher CMTI.
Frequent hot-plug, live service, complex power-down paths.
Need for forensics: reverse/backfeed logs; PG/Alert timestamp reconstruction.

Fail-Safe Logic

Define idle-high or Hi-Z for power-up/down/brown-out/single-side loss.
Independent pull-ups on both sides to maintain open-drain behavior and rise-time budgets.
Clock-stretching preserved across isolation.
No backfeed on power-down: reverse shut-off, measurable off-leakage, event logging.

System map (3:2): Telemetry Island (3.3 V) centered, Power Domain A/B on sides, dashed Isolation Moat between; annotated with Vdiff, I_leak, UVLO, dV/dt, CMTI. — Figure 2 — Telemetry-island vs. power-domain boundary (3:2)

Working Principle

System diagram of isolated PMBus with reverse/backfeed block and controlled startup (3:2). — System diagram: isolated PMBus/SMBus, back-to-back FET ideal-diode stage, and UVLO/PG/dV/dt governance.

Isolation Channel

Bidirectional open-drain reconstruction preserves I²C semantics across isolation. SDA/SCL are rebuilt with threshold/edge sensors; ALERT/PG are typically unidirectional. Independent pull-ups on both sides ensure predictable idle and cold-start behavior with high CMTI.

Tunable: pull-ups per side, bus capacitance budget, channel delay/power trade.
Measure: tPLH/tPHL, rise/fall, CMTI, off-leak.
Pitfall: large cold pull-ups + accumulated delay → Fm+ timing edge.

tPLH/tPHL [ns] CMTI [kV/µs] I_leak(off) [µA]

Reverse/Backfeed Blocking

Back-to-back MOSFETs with ideal-diode control shut off on reverse differential Vdiff and minimize forward drop. Validate off-leakage, reverse shut-off time, and i²t against SOA; verify connector-side paths for hidden backfeed.

Tunable: FET R_DS(on), controller thresholds/hysteresis, copper/through-vias for heat.
Measure: Vdiff, I_leak(off), reverse shut-off time, i²t.
Pitfall: near-zero Vdiff loop instability → low-frequency howl.

Vdiff [mV] I_leak(off) [µA] i²t / SOA

Controlled Startup

UVLO/OVLO windows with 3–5% hysteresis, slew-limited ramps, and PG/Alert alignment produce deterministic bring-up and auditable logs. Widen narrow PG pulses if upper layers require minimum width.

Tunable: UVLO/OVLO thresholds, hysteresis & debounce (≥1–5 ms), ramp dV/dt, PG delay/width.
Measure: UVLO_hi/lo, dV/dt, PG delay, Alert alignment.
Pitfall: mis-coordinated ramp vs isolator delay → false PG.

UVLO [%] / ms dV/dt [V/ms] PG delay [ms]

Failure Modes & Mitigation

Single-sided power loss → define fail-safe (Hi-Z or idle-high).
ESD-induced sticky-low → recovery path + watchdog; staged pull-ups if needed.
CMTI false triggers → guard traces/return reference/common-mode choke; run injection tests.
Hidden backfeed paths → audit connectors, aux supplies, debug ports.

Sticky_low_events CMTI_error_cnt Backfeed_event_cnt

Technical Breakdown

I²C timing windows through isolation (3:2): tPLH/tPHL, rise/fall, stretch; cold/hot curves. — 4A — I²C bidirectional timing windows across isolation.

Ideal-diode control loop from Vdiff to FET gate (3:2); small-signal stability near Vdiff≈0. — 4B — Ideal-diode loop: Vdiff → Vgs; small-signal stability near zero.

UVLO window and dV/dt with PG/Alert alignment (3:2). — 4C — UVLO windows, slew-limited ramp, and PG/Alert timing alignment.

Isolation Physics

Capacitive/magnetic/optical coupling; VIORM/VISO/Surge classes; lifetime and drift vs temperature. Prefer higher CMTI with lower delay and leakage; validate at temperature corners.

Compliance: creepage/clearance, pollution level, altitude derating.
Verify: dielectric withstand, CMTI injection, delay-vs-temp curves.

I²C Bidirectionality

Honor timing windows and clock-stretching; budget rise-time per side with independent pull-ups. Validate at 100/400/1M across cold/hot/long-trace/high-cap loads.

Mode	Rise/Fall Budget	tPLH/tPHL Target	Stretch Behavior
Standard/Fast	Per-side pull-ups sized for bus C	Keep margins vs spec min/max	Transparent across isolation
Fm+ (1 MHz)	Minimize RC; avoid overshoot/ringing	Aggregate delay < timing edge	No spurious holds on cold start

Fail-Safe Matrix

Define outputs for power-up, power-down, brown-out, and single-sided loss: idle-high or Hi-Z. Document and verify; forbid ambiguous states that can create false PG.

Idle policy: explicit and testable.
Separate pull-ups avoid cross-domain contention.

Reverse/Backfeed Loop

Control law from Vdiff to FET gate requires phase margin near zero differential. Sweep/step the loop; measure reverse shut-off, off-leak, and i²t; correlate with thermal Z_th.

Controlled Startup

Set UVLO thresholds with 3–5% hysteresis and 1–5 ms debounce; shape ramp dV/dt; align PG/Alert to the system cadence; widen PG pulses if required by the supervisor.

Safety & Layout

Honor creepage/clearance, pollution level, altitude rules. Keep isolation slots clean; prohibit return currents bridging the moat; avoid stitching vias across the gap.

Immunity

CMTI injection (10–20 ns edges), ESD/surge discharge paths, guard traces, return reference, and common-mode chokes. Track CMTI_error_cnt and false alerts; provide mitigation if any recurrence.

Key Metrics

Metric	Measurement Script	Pass Gate
Isolation.VIORM_working_V	Reference datasheet working isolation voltage; verify with dielectric withstand at temp corners.	Meets declared VIORM across temp; no partial discharge.
Isolation.VISO_withstand_V	Apply specified isolation test per standard; record leakage & breakdown.	No breakdown; leakage ≤ spec.
Isolation.Surge_kV	Surge test per applicable level; count failures, log waveforms.	Pass declared surge class; zero latent faults.
Isolation.CMTI_kVus (primary KPI)	Fast dv/dt injector (10–20 ns edges) across isolator; monitor false alerts/bit errors; sweep amplitude.	Target ≥ 100; Pass ≥ 50 kV/µs (full temp).
Isolation.Delay_tPLH_ns	Propagate low→high across isolation; oscilloscope time delta @ Fm+ load.	Each path ≤ 120 ns (keeps 1 MHz margins).
Isolation.Delay_tPHL_ns	Propagate high→low across isolation; same fixtures as above.	Each path ≤ 120 ns.
Isolation.I2C_mode_support (Std/Fm/Fm+)	Run 100/400/1M across cold/hot/long-C; verify stretch transparency and duty.	All modes pass with margins; no spurious holds at cold.
Isolation.Fail_safe_mode (idle-high/Hi-Z)	Ramp up/down & single-side-off; confirm defined idle on both sides with independent pull-ups.	No stuck bus / false PG under any ramp.
Protection.RDSon_mOhm_perFET (×2 for back-to-back)	4-wire measure at operating temp; include PCB copper heating in model.	Target 2–6 mΩ (per FET), thermally verified.
Protection.I_rev_leak_off_uA	Power-down; bias reverse; measure off-leak at connector and local rails.	Pass ≤ 10–50 µA (per voltage class).
Protection.Reverse_shutoff_us	Apply −V step; capture Vdiff and channel current; measure shut-off to safe region.	Pass ≤ 2–10 µs (no overshoot).
Protection.i2t_pulse_A2s	Compute ∫I²dt for worst pulses; correlate with thermal Z_th and camera.	Within SOA at ambient and corner temps.
Protection.SOA_crossing_point	Overlay operating/abuse pulses on SOA; flag crossings.	No SOA crossing under specified events.
Protection.Vdiff_trip_mV	Sweep small Vdiff; find trip & hysteresis; ensure stability near 0 mV.	Predictable trip; no low-freq howl.
Startup.UVLO_hi_V / UVLO_lo_V	Soft-ramp; timestamp hi/lo crossing; compute hysteresis %.	Within spec; consistent across temp/lot.
Startup.UVLO_hysteresis_pct	From hi/lo; validate during repeated ramps with noise injected.	Pass 3–5% (with debounce).
Startup.Debounce_ms	Hold off time around threshold; verify no chatter PG.	Pass ≥ 1–5 ms.
Startup.dVdt_V_per_ms	Program ramp slope; measure overshoot & settling; log PG timing.	Within window; no false PG/Alert.
Startup.PG_delay_ms	Δt from UVLO_hi to PG assert at target dV/dt.	Inside spec window (e.g., 5–50 ms).
Startup.Alert_align_ms	Resample to 1 kHz cadence; compare PG/Alert timestamps.	Alignment within ±1–2 ms; no micro-glitches.
Reliability.Delay_drift_ppm_perC	Sweep temperature; fit delay vs °C; record ppm/°C.	Within timing budget across temp.
Reliability.CMTI_drift_pct_over_temp	Re-run CMTI at temp corners; compare margin.	No catastrophic drop; remains ≥ pass level.
Reliability.Theta_JA_C_per_W	Steady dissipation test; correlate board stack-up to θ_JA.	Meets thermal budget at max power.
Reliability.Theta_JC_C_per_W	Package-to-case characterization; confirm heatsinking path.	Consistent with datasheet & model.
Reliability.Lifetime_FIT_or_hours	Use vendor reliability data; map to mission profile.	Meets program target FIT/hours.
Reliability.Humidity_Salt_factor (if applicable)	Run humidity/salt-fog as required; verify no leakage drift or corrosion paths.	No abnormal drift; passes visual/ESD retest.

Design Guidelines

Use independent pull-ups per side

Preserve open-drain semantics and rise-time budgets across isolation.

Quick Check: verify SDA_rise_ns at 100/400/1M.
Fields: tPLH/tPHL, SDA_rise_ns.

Validate stretch and jitter at 100/400/1M

Fm+ margins are delay-critical, especially at cold and with large C loads.

Quick Check: scope clock-stretch transparency and duty.
Fields: tPLH/tPHL, I2C_mode_support.

Document fail-safe states

Define outputs for power-up/down, brown-out, and single-sided loss (idle-high or Hi-Z).

Quick Check: simulate ramps; confirm no stuck bus / false PG.
Fields: Fail_safe_mode, Sticky_low_events.

UVLO with 3–5% hysteresis + 1–5 ms debounce

Suppress threshold chatter and de-glitch PG/Alert during ramps.

Quick Check: log UVLO_hi/lo; verify PG stability.
Fields: UVLO_hysteresis_pct, Debounce_ms.

Thermal & SOA for back-to-back FETs

Pulse heating dominates during reverse events; verify i²t and Z_th.

Quick Check: correlate IR camera with model.
Fields: RDSon_mOhm_perFET, i2t_pulse_A2s.

Stabilize the ideal-diode loop near Vdiff≈0

Ensure phase margin to avoid low-frequency howl or ringing.

Quick Check: small-signal sweep; reverse shut-off time.
Fields: Vdiff_mV, Reverse_shutoff_us.

Honor isolation slots and return paths

Keep the moat clean; forbid stitching vias or cross-slot returns.

Quick Check: visual DRC of slot integrity and guards.
Fields: CMTI_kVus.

CMTI hardening near switching nodes

Use guard traces, reference returns, and common-mode chokes; run dv/dt injection.

Quick Check: track CMTI_error_cnt.
Fields: CMTI_kVus, CMTI_error_cnt.

Align PG/Alert to a common cadence

Resample to 1 kHz (example) for deterministic bring-up and unified logs; widen narrow pulses.

Quick Check: PG_delay_ms, Alert_align_ms within window.
Fields: PG_delay_ms, Alert_align_ms.

DFM/Test hooks for evidence

Provide loopback across isolation, VDS/VGS pads, and reverse-event counters for field forensics.

Quick Check: hooks reachable; logging fields mapped.
Fields: Backfeed_event_cnt, I_leak_off_uA.

Layout dos/don’ts (3:2): keep the isolation slot clean with separated returns; avoid cross-slot return or coupling. — Figure 6 — Layout do/don’t for isolation slot and return paths.

Troubleshooting Matrix

Symptom	Observable Fields	Remedy
I²C sporadic NACK at cold	SDA_rise_ns, tPLH_ns, tPHL_ns, I2C_mode_support	Tune independent pull-ups both sides (reduce RC/overshoot), verify aggregated delay vs Fm+ margins, re-test clock-stretch transparency at cold.
Bus stuck low on power-up	Sticky_low_events, UVLO_hysteresis_pct, Debounce_ms	Document fail-safe states; increase UVLO hysteresis (3–5%) and debounce (≥1–5 ms); consider staged pull-ups or bring-up order.
Device heating after reverse event	Vdiff_mV, I_leak_off_uA, Reverse_shutoff_us, i2t_pulse_A2s, Tj_C	Shorten reverse shut-off; verify i²t vs SOA; add copper/thermal vias; select lower R_DS(on) FETs or spread heat path.
Ghost voltage after power-down (backfeed)	I_leak_off_uA, Backfeed_event_cnt	Audit connector/aux supply/debug-port paths; place ideal-diode controller at connector; minimize off-leak; speed up reverse shut-off.
Startup oscillation / PG chatter	UVLO_hi_V, UVLO_lo_V, UVLO_hysteresis_pct, dVdt_Vms, PG_delay_ms	Set 3–5% UVLO hysteresis + 1–5 ms debounce; limit dV/dt; widen PG pulses and align to system cadence.
False alert under CMTI injection	CMTI_kVus, CMTI_error_cnt	Add guard traces/return reference/CM choke; route away from fast dv/dt; validate to target CMTI class.
Lost alarm across isolation	tPLH_ns, tPHL_ns, Alert_align_ms	Confirm channel direction (ALERT/PG often unidirectional); unify time base (e.g., 1 kHz); widen narrow pulses.
Excess thermal rise on protection FETs	Theta_JA_C_per_W, Tj_C, i2t_pulse_A2s	Increase copper/thermal vias; check SOA crossing; distribute current; select lower R_DS(on).
PG jitter vs I²C activity	PG_delay_ms, SCL_duty_pct, tPLH_ns, tPHL_ns	Decouple PG harness from I²C; retune pull-ups and RC; align timing base across domains.
Connector hot-plug resets telemetry	Vrail_dVdt, UVLO_hysteresis_pct, CMTI_error_cnt	Limit dV/dt; increase UVLO debounce; add connector-side ideal-diode + TVS; route away from switching edges.
Long-cable ringing affects Fm+	SDA_rise_ns, SCL_duty_pct, tPLH_ns, tPHL_ns	Increase series damping or tweak pull-ups; verify eye window at 1 MHz; keep isolation slot and returns clean.
Alert polarity mismatch across domains	Alert_align_ms, tPLH_ns	Normalize polarity at the receiver; confirm one-way channel mapping; apply pulse stretcher if needed.
Brown-out on one side only; inconsistent fail-safe	UVLO_hi_V, UVLO_lo_V, Fail_safe_mode	Define explicit idle-high/Hi-Z; tighten UVLO window; isolate pull-ups to avoid cross-domain contention.
Reverse leakage wakes upstream PMIC	I_leak_off_uA, Backfeed_event_cnt	Reduce off-leak path; re-locate ideal-diode controller; add bleed/load gating; verify no backfeed through debug/aux lines.

Applications & Reference Schematics

A. Isolated PMBus Island

3.3 V both sides with independent pull-ups; ch0/1 → SDA/SCL (bidirectional), ch2 → ALERT (unidirectional); UVLO=3.05 V, hysteresis=120 mV, PG delay≈5 ms.

Application (3:2): isolated PMBus island with independent pull-ups, UVLO gate and 5 ms PG delay. — Figure 8A — Isolated PMBus island.

Key parameters: I2C_mode_support 100/400/1M; UVLO window with debounce; PG delay ≈ 5 ms.
Test points: SDA_rise_ns, tPLH/tPHL, Alert_align_ms (cold/hot/long-trace).
Log fields: Sticky_low_events, PG_delay_ms, Alert_align_ms.

B. Reverse/Backfeed-Protected Telemetry Rail

12 V rail with back-to-back MOSFETs (≤5 mΩ × 2) and ideal-diode controller; connector-side placement with thermal spreaders.

Application (3:2): telemetry rail with back-to-back FETs and ideal-diode controller; reverse shut-off < 1 µs, off-leak < 5–10 µA. — Figure 8B — Telemetry rail with reverse/backfeed protection.

Key parameters: Reverse_shutoff < 1 µs; I_leak(off) < 5–10 µA; controlled start dV/dt ≈ 0.5 V/ms.
Test points: Vdiff_mV, I_leak_off_uA, Reverse_shutoff_us, i2t_pulse_A2s; correlate with thermal Z_th.
Log fields: Backfeed_event_cnt, Tj_C.

C. Backfeed-Free Multi-Board Connector

Place ideal-diode controller at the connector; add thermal pads; audit cross-board backfeed paths; count events locally.

Application (3:2): connector-side ideal-diode control with local sensing and event logging; PG/Alert preserved. — Figure 8C — Backfeed-free multi-board connector.

Key parameters: I_leak(off) within class; no overheating on fast reverse; PG/Alert intact.
Test points: TP_Vdiff, TP_PG, Reverse_shutoff_us, Alert_align_ms.
Log fields: Backfeed_event_cnt, CMTI_error_cnt.

Reference ICs & CTA

Neutral checklist for datasheet cross-check

Use this to compare candidates for isolation, reverse/backfeed blocking, and controlled startup. Keep scope strictly to this subpage—no cross to siblings.

Isolation (I²C/SMBus/PMBus/GPIO)

VIORM / VISO, surge class, CMTI
Bidirectional I²C support, fail-safe behavior
Channel delay / jitter, Fm+ (1 MHz) capability
Channels, package, quiescent power

Reverse / Backfeed Blocking

Reverse shut-off time, off-leak current
Threshold accuracy, V_diff control
External FET R_DS(on), i²t vs SOA

Controlled Startup

UVLO/OVLO range & accuracy, hysteresis
dV/dt control window
PG/Alert logic & alignment

Safety / Layout / Reliability

Creepage/clearance, pollution level, altitude
Package pitch, θ_JA/θ_JC
Validation: timing/eye, CMTI injection, reverse events, thermography

Selection checklist for isolators and protection helpers (3:2) showing grouped fields for Isolation, Reverse/Backfeed, Controlled Startup, and Safety/Layout. — Figure 9 — Selection checklist (visual schema).

A) I²C Isolators (bidirectional open-drain)

Prefer parts that maintain I²C semantics across isolation with predictable fail-safe and Fm+ headroom.

Analog Devices ADuM2250 / ADuM2251

I²C-specific isolation; bidirectional SDA/SCL; variants compatible with up to 1 MHz; strong CMTI class options.

I²C 100/400/1M Fail-safe CMTI class

Texas Instruments ISO1640 / ISO1641 (incl. Q1)

Enhanced EMC I²C isolators; 1640 supports bidirectional clock; 1641 with defined direction; options for 3–5 kVrms isolation.

Fm+ ready Fail-safe EMC-hardened

Texas Instruments ISO1540 / ISO1541

Proven low-power I²C isolators for SMBus/PMBus with stable timing and clear power-up behavior.

Low power Bidirectional

Skyworks (ex-SiLabs) Si8600 / Si8602 / Si8605 / Si8606

I²C-focused isolators with strong CMTI; some AEC-Q100 options; wide supply combinations.

CMTI class AEC-Q100 (sel.)

B) Reverse / Backfeed Blocking (ideal-diode & controllers)

Choose parts that cut reverse current quickly, minimize off-leak, and support low total R_DS(on) with external MOSFETs.

Analog Devices LTC4357

High-voltage ideal-diode controller for N-MOS ORing and backfeed blocking.

Fast reverse cut Low off-leak

Analog Devices LTC4359

Ideal-diode controller with reverse input protection; robust at light load.

Reverse protected Back-to-back FET

Analog Devices LT8672

Active rectifier targeting reverse protection with rapid response to negative inputs.

µs-class shut-off Min drop

Analog Devices LTC4368-1 / LTC4368-2

Bidirectional e-switch controller with UV/OV thresholds and reverse blocking using back-to-back MOSFETs.

UV/OV guard Events ready

Texas Instruments LM5050-1 / LM5050-2

High-side ORing FET controllers (5–75 V) with fast reverse current cutoff.

High-side Fast cut

C) Controlled Startup (UVLO/OVLO + dV/dt + PG)

Focus on programmable UVLO/OVLO accuracy, ramp shaping, and clean PG/Alert alignment.

Analog Devices LTC4365

OV/UV protector with reverse guarding; wide tolerance to input transients; clean enable gating.

UV/OV set Reverse guard

Analog Devices LTC4367

Low-IQ surge/OV/UV protection; withstands large input transients while maintaining controlled startup.

Surge tolerant Low IQ

Texas Instruments TPS25982

Smart eFuse with programmable dV/dt, UV/OV thresholds, and PG—use as a reference for small telemetry rails.

dV/dt control PG output

Maxim Integrated (ADI) MAX17612A/B/C

4.5–60 V protection switch with programmable current limit and UV/OV—good for controlled bring-up on aux rails.

UV/OV set Limit/PG

Get the multi-brand equivalence map & validation scripts

Send your short-list and BOM. We’ll return a checklist→scripts→pass-gate bundle, including Fm+ timing windows, CMTI injection steps, reverse shut-off/i²t templates, and PG alignment macros.

Request equivalence map Submit BOM for pre-audit

Validation & Measurement Plan

I²C eye diagram and timing windows across isolation (3:2). — 10A — I²C eye/timing windows across isolation.

CMTI injection fixture with observation nodes (3:2). — 10B — CMTI injection fixture and observation nodes.

Reverse/backfeed and controlled startup timing (3:2). — 10C — Reverse/backfeed and controlled startup timing.

10.1 I²C side

Scope I²C semantics through isolation at 100/400/1 MHz with cold/hot/long-trace/large-C extremes.

Equipment

≥500 MHz oscilloscope + logic analyzer
Programmable pull-up array (2–10 kΩ)
Thermal chamber (−40 °C / +85 °C)

Steps & Pass

Sweep pull-ups and cable C; log tPLH/tPHL, rise/fall, SCL duty, and stretch transparency. Pass: Fm+ eye/timing margins hold; no stuck-low.

tPLH/tPHL SDA_rise_ns I2C_mode_support

10.2 CMTI injection

Use a fast dv/dt neighbor board (10–20 ns edges) to inject common-mode transients and track false activity.

Fixture & Steps

Place injector parallel to isolated harness
Sweep amplitude & edge; record errors
Repeat at temp corners

Log & Pass

Log: CMTI_kVus, CMTI_error_cnt, Sticky_low_events. Pass: Target CMTI level (≥50–100 kV/µs) without false alerts.

10.3 Reverse / backfeed

Apply negative step to the 12 V telemetry rail; measure shut-off dynamics and leakage under room/hot conditions.

Steps

Capture Vdiff and channel current
Measure Reverse_shutoff_us & I_leak_off_uA
Thermal camera vs Z_th model

Pass

Reverse shut-off < 1 µs, off-leak < 5–10 µA, no “ghost” wake-ups; i²t within SOA.

10.4 Controlled startup

Program UVLO_hi/lo and hysteresis (3–5%); scan ramp slope; time-align PG/Alert to the system cadence.

Steps

Set UVLO thresholds & debounce (≥1–5 ms)
Program dV/dt; capture PG_delay_ms & Alert_align_ms
Verify no oscillation near thresholds

Pass

PG/Alert aligned (±1–2 ms) to the chosen cadence; no chatter; no backfeed on power-down.

10.5 Thermal & SOA

Exercise 10 ms → 1 s pulses and correlate junction rise with Z_th curves; verify i²t margins.

Steps

Pulsed load sweep (amplitude × duration)
Record Tj_C and map to Z_th(j-a)
Check SOA crossings; adjust copper/vents

Pass

Worst-case Tj below limit; no SOA violations; thermal camera consistent with model.

Field	Description	Notes
tPLH_ns / tPHL_ns	Propagation delays across isolation	Record per direction and temperature
SDA_rise_ns, SCL_duty_pct	Rise time and duty cycle under chosen pull-ups	Note cable C and mode (100/400/1M)
CMTI_kVus, CMTI_error_cnt	dv/dt level and false-event counter	Log injector edge ns and amplitude
Reverse_shutoff_us, I_leak_off_uA, Vdiff_mV	Reverse blocking dynamics and leakage	Room/hot; connector-side paths audited
UVLO_hi_V / UVLO_lo_V / UVLO_hysteresis_pct	Bring-up thresholds and hysteresis	Debounce ≥ 1–5 ms
dVdt_Vms, PG_delay_ms, Alert_align_ms	Ramp slope, PG delay and Alert alignment	Align to system cadence (e.g., 1 kHz)
Backfeed_event_cnt, Theta_JA_C_per_W, Tj_C	Backfeed statistics and thermal margins	Cross-check with i²t & Z_th

FAQ

How is fail-safe power-up guaranteed?

Fail-safe behavior is defined per side: idle-high or Hi-Z with independent pull-ups. Use a UVLO window with 3–5% hysteresis and 1–5 ms debounce so SDA/SCL/PG don’t chatter near thresholds. Validate single-sided loss and brown-out. If needed, issue a bus-clear on bring-up and document expected levels in the interface spec.

Does Fm+ (1 MHz) lose margin to isolation delay?

Budget the aggregate tPLH/tPHL and rise-time per side. Keep each propagation path ≤ ~120 ns and meet rise-time targets with appropriate pull-ups. Verify clock-stretch transparency at cold and with long cables. Use eye/timing windows at 1 MHz to confirm there is still duty-cycle and setup/hold margin after isolation.

How much CMTI is “enough”?

For noisy power planes, target ≥ 100 kV/µs; ≥ 50 kV/µs is a practical pass gate across temperature. Validate with a fast dv/dt injector and log CMTI_kVus and CMTI_error_cnt. If transient-induced alerts appear, add guard traces, a defined return reference, or a common-mode choke and re-test at the same stress level.

How do I completely block backfeed?

Place an ideal-diode controller at the connector with back-to-back MOSFETs. Aim for Reverse_shutoff_us < 1 µs and I_leak_off_uA < 5–10 µA. Audit alternate paths (aux rails, debug ports, remote-sense lines). Disable pull-ups from a dead domain and confirm no “ghost voltage” during power-down in hot-plug conditions.

Can back-to-back FETs survive short pulses?

Check the SOA using i²t and transient Zth(j-a) curves. Exercise 10 ms to 1 s pulses and correlate with thermal imaging. Reduce RDSon or add copper/thermal vias if Tj trends high. Ensure the ideal-diode control loop is stable near Vdiff ≈ 0 mV to avoid low-frequency howl during boundary operation.

What hysteresis should I set for UVLO?

Use 3–5% hysteresis with ≥ 1–5 ms debounce to suppress threshold chatter and false PG. Place the UVLO window outside expected droop during inrush and transients. Validate across temperature and line steps. Record UVLO_hi_V/UVLO_lo_V and UVLO_hysteresis_pct to prove repeatable bring-up.

How do I align PG/Alert across isolation?

Resample to a common cadence (e.g., 1 kHz) and timestamp both sides. Widen narrow pulses so they survive propagation delay and filtering. Map channel direction explicitly (ALERT/PG are often unidirectional). Track PG_delay_ms and Alert_align_ms and keep alignment within ±1–2 ms under nominal ramps.

What should I do if the bus sticks low after ESD?

Power-cycle the impacted side, then verify documented fail-safe states. Add series damping or an ESD/TVS device at the connector, and increase debounce around UVLO. Implement an I²C bus clear procedure on start-up. Log Sticky_low_events to identify sporadic latch-ups after ESD or surge hits.

How do I size pull-ups on both sides of isolation?

Keep pull-ups independent per side. Size for the target mode: start around 2–4 kΩ @ 3.3 V and tune for rise-time on long cables or high C loads. Avoid cross-domain ties that defeat isolation semantics. Re-verify at 100/400/1000 kHz and at cold corners to ensure duty and setup/hold margins remain.

How do I record evidence of reverse events?

Expose a non-volatile Backfeed_event_cnt and timestamp each reversal. Log Vdiff_mV, I_leak_off_uA, and local Tj_C near the FETs. On retrieval, correlate with power-down logs to confirm no “ghost wake-ups.” Provide a PMBus register map so field tools can export the evidence for root-cause analysis.

When is “reinforced isolation” required?

Use reinforced isolation when safety standards, high VIORM, or medical/automotive categories apply. Consider altitude and pollution degree for creepage/clearance. Verify VISO and surge class against the mission profile. If in doubt, choose reinforced packages and maintain the PCB isolation slot with documented keep-outs.

What are the isolation-slot layout no-go zones?

Do not place stitching vias or return traces across the slot. Keep high dv/dt switch nodes and inductors away from the moat. Add guard traces with a defined reference. Maintain required creepage/clearance, and avoid sensors crossing the gap. Place TVS and connectors thoughtfully to prevent unintended common-mode coupling.