PG Aggregators & Voters | Power Integrity

PG Aggregators & Voters condense many Power-Good/alert (PG/FAULT) lines into one trustworthy “system-ready” or “any-fault” signal for multi-rail power systems, reducing MCU/SoC timing complexity.

By unifying polarity/levels and applying deglitch, delay/hold, and AND/OR/N-of-M majority decisions—then driving with push-pull or open-drain buffers—these helpers harden long, noisy buses and deliver consistent interlocks without crossing into sequencers or ADC monitors.

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Browse sections

1 Answer Box 2 What is it 3 Working Principle 4 Technical Breakdown 5 Key Metrics 6 Design Guidelines 7 Troubleshooting Matrix 8 Applications & Schematics 9 Reference Implementations 10 FAQ

Answer Box (Decision Snapshot)

PG aggregator quick picks: AND/OR/Majority with deglitch, delay and driver sliders — Cover card: three micro-circuits (All-Good / Any-Fault / 2-of-3 Majority) + parameter sliders.

Positioning: Consolidate multiple PG/Alert lines into a single trustworthy system-ready or fault signal to simplify MCU/SoC timing and interlocks.

Systems with 2–20 PG/Alert lines requiring All-Good (AND) or Any-Fault (OR).
Redundant/forgiving designs that need N-of-M majority voting (e.g., 2-of-3, 3-of-5).
Cross-board or long-trace wiring where bus edges are slow/noisy → add deglitch, delay, and strong drive.

✅ All-Good (Power-Up Ready)

Open-drain PG wired-AND + single pull-up → Schmitt buffer → power-up/down delay → push-pull output.

Wired-AND Schmitt Delay Push-pull

Long traces/heavy bus capacitance → add a post-merge driver or retimer.

✅ Any-Fault (Immediate Alert)

FAULT# wired-OR (tie + pull-up) → deglitch/min-pulse → push-pull or open-drain output.

Wired-OR Deglitch Min-pulse

Stretch short faults so the MCU can reliably capture the interrupt.

✅ N-of-M Majority (2-of-3 / 3-of-5)

Small LVC logic; or star-resistor summing + comparator + VREF (supports weighting/masking).

N-of-M Comparator VREF Mask/Weight

Budget tolerance/thermal drift; keep a VETO path for lethal faults.

What is it (Definition & Scope)

Definition: A PG Aggregator & Voter unifies multiple PG/Power-Good/Alert lines by normalizing polarity and logic levels, applying deglitch and delay, and performing logical voting (AND/OR/N-of-M) to output a single reliable system-ready or fault signal.

Input forms

Open-drain/open-collector or push-pull; Active-High PG vs Active-Low FAULT#.
Mixed logic domains (1.2/1.8/3.3/5 V): level align and unify polarity before voting.
Prefer Schmitt inputs for better noise immunity and stable thresholds.

PG/FAULT input map: polarity (Active-High/Active-Low) vs driver (OD/PP) with mini waveforms and interface

Output forms

Push-pull: best for long-trace robustness and fast edges.
Open-drain: convenient for wired logic or shared low-true lines.
Define known power-up state; respect UVLO/ESD limits within the chosen logic domain.

Output choice: open-drain for wired logic vs push-pull for long-trace robust edges

Boundary (non-overlap with sibling pages)

No multi-rail telemetry/ADC sampling (covered elsewhere).
No full power-up/down sequencing trees (covered elsewhere).
No event logging/thermal/EMI topics (covered elsewhere).

Working Principle

Input Qualifier

Polarity unify; level align (1.2/1.8/3.3/5 V); Schmitt + RC or digital counter deglitch.

➜

Voter Core

AND / OR, N-of-M, optional weighting/masking; VETO high-priority override.

➜

Timing Domain

Deglitch window, min-hold, power-up/down delay, pulse stretch.

➜

Output Driver

Push-pull (long trace, fast edges) or open-drain (wired logic); deliver SYS_PG / ANY_FAULT to MCU/SoC.

RC deglitch (rising edge)

V(t) = VDD(1 − e−t/τ)
Reject a pulse width tp if: V(tp) < VTH+ ⇒ τ > tp / ln( 1 / (1 − VTH+/VDD) ).

Use Schmitt inputs with RC for robust thresholds and hysteresis.

Wired bus edge (AND/OR)

tr ≈ 2.2 · RPU · CBUS

Long traces and multiple ties increase C_BUS → use stronger pull-up or add a buffer/retimer.

2-of-3 majority (resistor star + comparator)

V+ = (nHIGH/3) · VH, choose VREF = 0.5 · VH → pass only when 2/3 are high.
Noise margin = (1/6) · VH.

Extend to N-of-M via weighting (resistor ratios/current sources) and per-channel masking.

Wired-AND All-Good: multiple open-drain PG, single pull-up, Schmitt buffer, push-pull output — Fig. 3A — Wired-AND (All-Good)

Wired-OR Any-Fault: FAULT# ties with pull-up, deglitch window, MCU capture — Fig. 3B — Wired-OR (Any-Fault)

2-of-3 majority by resistor star and comparator; VREF around half of VH; optional delay — Fig. 3C — 2-of-3 Majority

Timing shaping: deglitch threshold, minimum hold, power-up release overlays — Fig. 3D — Timing Shaper

Long-trace driver: post-merge buffer yields sharper edges over 50–200 cm harness — Fig. 3E — Long-Trace Driver

Technical Breakdown

Input Qualifier

Polarity unify: choose “logic-true = good” or the opposite and stick to it.
Level align: clamp/translate between 1.2/1.8/3.3/5 V; normalize before voting.
Deglitch: RC + Schmitt (simple, robust) or digital counter/monoflop (programmable min-pulse).

Typical: 0.5–5 ms window based on upstream ripple & POR needs.

Voter Core

AND/OR: LVC gates (prefer Schmitt variants) or small programmable logic; OD buses can wired-AND/OR.
N-of-M: small M (≤4) via gates; scalable via resistor-sum + comparator + adjustable V_REF.
Mask/weight: per-channel bypass; weighting by resistor ratios or current sources.
VETO: lethal faults override majority and force fail-safe low.

Timing Domain

Power-up delay: release after all rails finish soft-start (add margin; typ. 1–20 ms).
Power-down delay: avoid repeat resets on brief droops (0.5–5 ms).
Min-hold: meet reset/POR width; stretch short alerts for MCU sampling.

Test with slow-ramp, short-drop, and ripple playback; watch for “reset storms”.

Output Driver

Push-pull for cross-board runs and sharp edges; open-drain for shared wired logic.
Edge control: t_r ≈ 2.2·R_PU·C_BUS; larger C_BUS → stronger pull-up or buffer/retime.
Drive budget: ≥ ±8 mA (long trace: ≥ ±24 mA). Define power-up state; respect UVLO/ESD of the chosen domain.

VETO path overrides majority: any lethal alert forces SYS_PG low immediately — Fig. 4 — VETO life-line (override majority)

RC selector: required time constant vs pulse width tp for several VTH/ VDD ratios — Fig. 5 — RC time-constant selector

Key Metrics

Use this template to capture per-design values. Keep units consistent, and record the target logic domain for each input.

Category

Input compatibility

Field

Type / Polarity

Typical / Recommended

OD/PP; unify H/L before voting; record each rail’s logic domain.

Notes

Normalize to “logic-true = good”. Level-shift across 1.2/1.8/3.3/5 V first.

Category

Threshold / Hysteresis

Field

VIL / VIH, ΔV_Hys

Typical / Recommended

Prefer Schmitt inputs; ΔV_Hys ≈ 0.1–0.2 · V_IO.

Notes

Hysteresis resists ripple and mid-level chatter on slow edges.

Category

Deglitch

Field

t_DEGLITCH

Typical / Recommended

0.5–5 ms (tune vs ripple/noise and POR needs).

Notes

Use RC + Schmitt or digital counter; reject narrow spikes reliably.

Category

Delays

Field

t_ON / t_OFF

Typical / Recommended

1–20 ms / 0.5–5 ms (align with POR and upstream soft-start).

Notes

Prevent “reset storms” on brief droops; release only when rails are stable.

Category

Majority voting

Field

N-of-M / Weights

Typical / Recommended

2-of-3, weights = 1 (mask/weight per channel as needed).

Notes

Keep a VETO path for lethal faults to override majority.

Category

Reference threshold

Field

V_REF (majority)

Typical / Recommended

Midpoint ≈ 0.5 · V_H (keep within (1/3, 2/3) · V_H).

Notes

Gives symmetric noise margin for 2-of-3 voting.

Category

Output

Field

Mode / Drive

Typical / Recommended

Push-pull ±8–24 mA (prefer for long traces); OD for wired logic.

Notes

Edge estimate for OD: t_r ≈ 2.2 · R_PU · C_BUS.

Category

Timing quality

Field

Minimum hold

Typical / Recommended

≥ 100 µs (meet POR/reset width; stretch short alerts).

Notes

Prevents edge-case false decisions at the boundary.

Category

Reliability

Field

UVLO / ESD / Temp

Typical / Recommended

Industrial / automotive grades; power-up known state.

Notes

Respect domain UVLO/ESD limits; verify across temperature.

Category

Layout

Field

Pull-up placement

Typical / Recommended

Place near aggregation node; keep the bus short and loop-closed.

Notes

Use a continuous return plane; via pairs across splits; VREF close to comparator.

Radar of noise immunity, scalability, area, and complexity across wired-logic, LVC gates, and comparator majority — Fig. 6 — Indicator radar: wired-AND/OR, LVC gates, comparator-based majority.

Design Guidelines

Separate outputs for All-Good and Any-Fault

Why: Clearer logic and isolation between ready and fault paths.

How: Export both SYS_PG and ANY_FAULT; let MCU build the state machine.

Pitfall: Merging into a single wire complicates debug and traceability.

Unify polarity & level before voting

Why: Reduces combinational complexity and corner cases.

How: Normalize to “logic-true = good”. Translate 1.2/1.8/3.3/5 V into the voter’s domain.

Pitfall: Mixing AH/AL or domains on a shared bus.

Prefer Schmitt + RC for deglitch; add digital min-hold if needed

Why: Handles both slow edges/ripple and narrow spikes.

How: Set 0.5–5 ms deglitch; ensure ≥100 µs minimum hold or pulse-stretching.

Pitfall: RC without hysteresis leads to threshold chatter.

Buffer after aggregation for long traces

Why: Wired buses increase C_BUS, slowing edges.

How: Use push-pull buffer/retimer; budget ≥ ±24 mA for long harnesses.

Pitfall: Slow edges cause mis-sampling and spurious faults.

2-of-3 majority: comparator + star resistors; set VREF ≈ 0.5·VH

Why: Symmetric noise margin with graceful fault tolerance.

How: Equal resistors to CMP+; mask/weight channels as needed; keep a direct VETO path.

Pitfall: V_REF too close to 1/3 or 2/3 reduces margin.

VETO overrides everything

Why: Lethal faults must force fail-safe low immediately.

How: Route VETO in parallel with the voter to the output OR; latch/hold as required.

Pitfall: Treating VETO as just another vote hides critical failures.

Align tON/tOFF with upstream rails & POR

Why: Avoid reset storms and false-ready conditions.

How: t_ON ≥ upstream soft-start + margin; t_OFF filters brief droops.

Pitfall: Ignoring remote load plug-in/out and soft-start variance.

Exercise injection tests per channel

Why: Boundary conditions expose real-world issues.

How: Inject slow-ramp, short-drop, stuck-low, stuck-high; sweep N-of-M combinations.

Pitfall: Testing only all-good/all-bad misses critical edges.

Log timing evidence for production

Why: Ensures consistency and traceability across units.

How: Capture key waveforms for each PG and SYS_PG; store with parameter snapshots.

Pitfall: Relying only on MCU logs without scope evidence.

Layout close-loop: pull-ups & VREF near the node

Why: Minimizes parasitics and crosstalk; improves timing determinism.

How: Keep a continuous return plane; use via pairs across splits; place pull-ups/VREF near the aggregator.

Pitfall: Scattered pull-ups across boards cause uncontrollable timing.

Troubleshooting Matrix

Close the loop for each symptom: Phenomenon → Possible Cause → Observation → Quick Fix.

Phenomenon

SYS_PG chatter

Possible cause

Slow bus edge / spikes: large C_BUS, pull-up too weak, crosstalk.

Observation

Shared-node waveform, estimate C_BUS, pre/post-buffer edge rate.

Quick fix

Add push-pull buffer/retimer; reduce R_PU; widen deglitch window.

Phenomenon

Intermittent reset storm

Possible cause

t_OFF too short; missing minimum hold/pulse stretch.

Observation

POR pulse width; relative timing of SYS_PG vs per-rail PG.

Quick fix

Increase t_OFF; add pulse stretcher ≥ 100 µs.

Phenomenon

Majority decision error

Possible cause

V_REF bias/tolerance, unequal star resistors, comparator input leakage.

Observation

CMP +/− levels; VH accuracy; stability of V_REF.

Quick fix

Tune V_REF ≈ 0.5·VH; use 0.5% resistors; revise weighting/mask.

Phenomenon

Wired-bus high level too low

Possible cause

R_PU too large; leakage; excessive C_BUS.

Observation

Bus DC level, rise time, sink/source current.

Quick fix

Reduce R_PU (e.g., 10 kΩ → 4.7/2.2 kΩ); buffer at aggregation node.

Phenomenon

Long-run false triggers

Possible cause

Crosstalk, ground bounce, discontinuous return paths.

Observation

Far-end waveform, coupling to neighbors, plane splits.

Quick fix

Twist/shield; close the return loop; use push-pull driver or retime.

Phenomenon

Power-up “false ready”

Possible cause

t_ON margin too small; rails not settled.

Observation

Phase of rail PG vs SYS_PG; slow-ramp playback.

Quick fix

Increase t_ON to exceed the slowest soft-start by 1–5 ms.

Oscilloscope snippets of six typical PG issues: chatter, false-ready, slow edge, droop, crosstalk, threshold grazing — Fig. 7 — Error waveform library: chatter, false-ready, slow edge, droop, crosstalk, threshold grazing.

Applications & Schematics

A. Single-board All-Good (wired-AND + buffer)

Multiple PG (OD, active-high) → wired-AND with pull-up to 3.3 V → Schmitt buffer → t_ON/t_OFF shaping (RC or monostable) → push-pull driver → MCU SYS_PG.

Reference values: R_PU=4.7 kΩ; RC = 100 kΩ // 47 nF (≈ 4.7 ms); drive ≥ ±8 mA (long run ≥ ±24 mA).

BOM (example MPNs)

Schmitt buffer (non-inverting): SN74LVC1G17DBVR (TI)
Open-drain buffer (optional isolation): SN74LVC1G07DBVR (TI)
Push-pull gate/buffer: SN74LVC1G125DBVR (TI)
Pull-up: RC0603FR-074K7L (Yageo, 4.7 kΩ)
RC (deglitch): CRCW0603100KFKEA (Vishay, 100 kΩ) + GRM188R71C473KA01 (Murata, 0.047 µF)

Validation checklist

Soft-start aligned: release after all rails are stable + 1–5 ms.
Minimum hold ≥ 100 µs.
Edge rate within MCU input limits.

All-Good aggregator: OD PG bus with pull-up, Schmitt buffer, delay, push-pull SYS_PG — Fig. 8A — All-Good aggregator schematic.

B. Any-Fault global alarm (wired-OR)

Multiple FAULT# (OD, active-low) → wired-OR with pull-up → deglitch + minimum-pulse shaping → MCU interrupt.

Reference values: t_DEGLITCH=0.5–5 ms; pulse-stretch to 1–5 ms for MCU capture.

BOM (example MPNs)

Dual open-drain combiner: SN74LVC2G07DBVR (TI)
Schmitt buffer (deglitch): SN74LVC1G17DBVR (TI) or inverting SN74LVC1G14DBVR
CMOS timer (monostable): TLC555CD (TI)
Pull-up: RC0603FR-072K2L (Yageo, 2.2 kΩ)
RC (deglitch): 100 kΩ + 47 nF (see 8A parts)

Validation checklist

Short-fault injection (10–200 µs) → 100% IRQ capture rate.
Rise-time matches estimate t_r ≈ 2.2 · R_PU · C_BUS.

Any-Fault aggregator: FAULT# wired-OR with pull-up, deglitch and min-pulse to MCU interrupt — Fig. 8B — Any-Fault aggregator schematic.

C. 2-of-3 redundant-supply majority voter

Three PG (active-high) → 3× equal resistors (star) → comparator +; − at V_REF ≈ 0.5·VH → delay → push-pull output.

Reference values: Star R = 100 kΩ ×3; V_REF by 2×100 kΩ divider; t_ON=5–10 ms.

BOM (example MPNs)

Comparator (open-drain): LMV331IDBVR or TLV7041IDBVR (TI)
Comparator (push-pull alt.): TLV3201AIDBVR (TI)
Precision reference (optional): TLV431AIDBZR (TI)
Precision resistors: ERA-3AEB1003V (Panasonic, 100 kΩ, 0.1%) ×5
Delay RC: CRCW0603100KFKEA (100 kΩ) + GRM188R71C103KA01 (0.01 µF)
Output buffer (long run): SN74LVC1G17DBVR / SN74LVC1G125DBVR (TI)

Validation checklist

Exhaustive 8-state sweep: output passes only when ≥2 inputs are high.
Temperature sweep (−40…+85 °C): threshold drift within margin.

2-of-3 majority: three equal resistors to comparator plus, VREF at half VH, delayed push-pull output — Fig. 8C — 2-of-3 majority voter schematic.

Request a Quote (RFQ)

Reference Implementations

Glue-class parts only (no sequencers, ADC monitors, or black-box recorders). Focus: polarity/level unification → voting → timing → drive.

Configurable single-gate logic (with Schmitt) — 1G97/1G98 class

1.65–5.5 V universal building blocks to realize AND/OR/NAND/NOR/INV by pin configuration. Schmitt inputs improve slow-edge immunity.

Use cases: compact All-Good/Any-Fault logic; small N-of-M (≤4) via multiple gates.
Example MPNs: SN74LVC1G97, SN74LVC1G98 (TI); 74AUP1G97 (Nexperia).
Tips: normalize polarity first; keep ΔV_Hys on inputs.

Push-pull buffers / inverters — LVC/HCS single-gates

Strong drive (±8–24 mA) for aggregation-point re-timing and long harnesses; Schmitt options for robust edges.

Example MPNs: SN74LVC1G17 (non-inverting Schmitt), SN74LVC1G14 (inverting Schmitt), SN74LVC1G125 (3-state).
When to use: wired buses with large C_BUS, cross-board signaling, noisy environments.

General-purpose comparators (for majority voters)

Star-resistor summing + comparator implements 2-of-3 / 3-of-5. Pick OD or push-pull outputs to match downstream drive.

Example MPNs: LMV331 / TLV7041 (OD, low power), TLV3201 (push-pull).
Reference options: TLV431 (programmable reference), or 0.1% divider for V_REF.

Passives — pull-ups, star resistors, RC deglitch

Pull-up R: 2.2–10 kΩ (size via t_r ≈ 2.2·R_PU·C_BUS).
Star resistors: 10–100 kΩ, 0.1–1% (match & thermal budget).
RC deglitch: 10–100 nF with 47–200 kΩ → 0.5–5 ms window.
Example MPNs: ERA-3A/ERA-6A (Panasonic 0.1%), CRCW0603 (Vishay 1%), GRM188 (Murata).

Three reference builds (minimal BOM)

R-1

All-Good (wired-AND + Schmitt + delay + push-pull)

PG(OD, AH) bus → pull-up 3.3 V → Schmitt buffer → t_ON/t_OFF → push-pull → MCU SYS_PG.

Reference values

R_PU=4.7 kΩ; RC=100 kΩ // 47 nF (≈4.7 ms).
Drive ≥ ±8 mA (long run ≥ ±24 mA).

Example BOM

SN74LVC1G17, SN74LVC1G125; optional SN74LVC1G07 (OD).
RC0603FR-074K7L; CRCW0603100KFKEA; GRM188R71C473KA01.

Validation

Release after all rails stable + 1–5 ms.
Min hold ≥ 100 µs; edges meet MCU spec.

R-2

Any-Fault (wired-OR + deglitch + minimum-pulse)

FAULT#(OD, AL) bus → pull-up → deglitch + pulse-stretch → MCU IRQ.

Reference values

t_DEGLITCH=0.5–5 ms; stretch to 1–5 ms if MCU needs.

Example BOM

SN74LVC2G07; SN74LVC1G17 or SN74LVC1G14.
TLC555 (monostable); RC0603FR-072K2L; RC/C as above.

Validation

10–200 µs faults → 100% capture.
Rise-time fits t_r ≈ 2.2·R_PU·C_BUS.

R-3

2-of-3 majority (star resistors + comparator + delay)

Three PG (AH) → 3× equal R (star) → CMP+; CMP− at V_REF≈0.5·V_H → delay → push-pull.

Reference values

Star R = 100 kΩ ×3; V_REF via 2×100 kΩ divider; t_ON=5–10 ms.

Example BOM

LMV331 / TLV7041 (OD) or TLV3201 (PP).
ERA-3AEB1003V (0.1% 100 kΩ) ×5; TLV431 (optional).
CRCW0603100KFKEA + GRM188R71C103KA01 for delay.

Validation

Exhaustive 8-state sweep: pass only when ≥2 are high.
−40…+85 °C: margin ≥ 10%·V_H.

Request a Quote (RFQ)

FAQ

Wired PG level is too low after OR/AND. What can I do?

Lower the pull-up value, buffer after aggregation, and check leakage/parallel loads. Verify rise time vs MCU spec using t_r ≈ 2.2·R_PU·C_BUS.

How do I support variable N in an N-of-M majority voter?

Use resistor-summing plus an adjustable reference (DAC/digipot), or switch weighted resistors to realize multiple thresholds (e.g., 1/2/3). Always keep a hard VETO path.

Will a PG line directly driving a downstream EN chatter?

Yes. Add deglitch (0.5–5 ms) and minimum hold (≥100 µs), and align t_ON/t_OFF to upstream soft-start to avoid false enables.

Which one has priority: majority decision or VETO?

VETO overrides the voter to guarantee fail-safe behavior. Consider latching VETO until a supervised clear to avoid oscillation.

Push-pull or open-drain at the output?

Use push-pull for long traces/remote boards (strong edges, lower susceptibility). Keep open-drain only when sharing a wired bus or mixing domains; then re-buffer locally.

How do I choose the pull-up resistor for a wired bus?

Estimate C_BUS, target an edge time meeting sink/source and input limits, and solve R_PU ≤ t_r/(2.2·C_BUS). Watch static power when R_PU is small.

What deglitch window should I start with?

Begin with 0.5–5 ms based on measured ripple/SSC and POR needs. Validate with slow-ramp and burst-noise injections; don’t over-filter genuine faults.

How should I pick VREF and tolerances for a 2-of-3 voter?

Set V_REF ≈ 0.5·V_H and keep it within (1/3, 2/3)·V_H. Use 0.1–0.5% matched resistors and budget temp-drift/offset so margin ≥ 10%·V_H.

How do I unify mixed polarities and logic domains safely?

Normalize polarity first (AH/AL) and level-shift early (1.2/1.8/3.3/5 V) via Schmitt gates or comparators. Respect UVLO/ESD limits and ensure a known power-up state.

How do I prevent long-run false triggers over a harness?

Close the return path (no split planes), twist/shield pairs, and re-time with a push-pull buffer at the aggregation node. Verify with neighbor-step injections.

Why do I see “reset storms” on brief droops and how to stop them?

t_OFF is too short or there is no minimum hold. Add a pulse stretcher (≥100 µs) and extend t_OFF so brief dips don’t retrigger POR.

Where should pull-ups and VREF networks be placed on the PCB?

Near the aggregation/comparator node with a continuous return plane. Use via pairs across plane splits; decouple the reference locally to minimize injected noise.

PG Aggregators & Voters for Clean, Reliable SYS_PG

Quick Browse

Answer Box (Decision Snapshot)

✅ All-Good (Power-Up Ready)

✅ Any-Fault (Immediate Alert)

✅ N-of-M Majority (2-of-3 / 3-of-5)

What is it (Definition & Scope)

Input forms

Output forms

Boundary (non-overlap with sibling pages)

Working Principle

Technical Breakdown

Input Qualifier

Voter Core

Timing Domain

Output Driver

Key Metrics

Design Guidelines

Troubleshooting Matrix

Applications & Schematics

A. Single-board All-Good (wired-AND + buffer)

B. Any-Fault global alarm (wired-OR)

C. 2-of-3 redundant-supply majority voter

Reference Implementations

Configurable single-gate logic (with Schmitt) — 1G97/1G98 class

Push-pull buffers / inverters — LVC/HCS single-gates

General-purpose comparators (for majority voters)

Passives — pull-ups, star resistors, RC deglitch

Three reference builds (minimal BOM)

FAQ

Related Articles

PG Aggregators & Voters for Clean, Reliable SYS_PG

Quick Browse

Answer Box (Decision Snapshot)

✅ All-Good (Power-Up Ready)

✅ Any-Fault (Immediate Alert)

✅ N-of-M Majority (2-of-3 / 3-of-5)

What is it (Definition & Scope)

Input forms

Output forms

Boundary (non-overlap with sibling pages)

Working Principle

Technical Breakdown

Input Qualifier

Voter Core

Timing Domain

Output Driver

Key Metrics

Design Guidelines

Troubleshooting Matrix

Applications & Schematics

A. Single-board All-Good (wired-AND + buffer)

B. Any-Fault global alarm (wired-OR)

C. 2-of-3 redundant-supply majority voter

Reference Implementations

Configurable single-gate logic (with Schmitt) — 1G97/1G98 class

Push-pull buffers / inverters — LVC/HCS single-gates

General-purpose comparators (for majority voters)

Passives — pull-ups, star resistors, RC deglitch

Three reference builds (minimal BOM)

FAQ

Related Articles

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