Power Monitors with ADC | Power Integrity Helper ICs

Power Monitors with ADC digitize rail V/I/P/E with programmable thresholds, ALERT (hysteresis, deglitch, latch), and bus readout over I²C/SMBus/PMBus. Design for fidelity with Kelvin sense, small RC, well-chosen t_conv/N, and robust logging: atomic energy reads, rollover accounting, and PEC/timeout handling for production and field evidence.

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Browse sections

1 Answer Box 2 What is it 3 Working Principle 4 Technical Breakdown 5 Key Metrics 6 Design Guidelines 7 Layout & EMI 8 Register & Data Model 9 Firmware Patterns 10 Calibration & Validation 11 Accuracy Budget 12 Production Test 13 Troubleshooting Matrix 14 Applications & Circuits 15 Reference ICs & BOM 16 FAQ

1) Answer Box | Decision Snapshot

6–8 punchy lines to clarify what it is, what it solves, how to select, how to deploy, and common pitfalls—so a team can start a selection review immediately.

What it is

An ADC-based power monitor that digitizes rail voltage/current/power/energy, exposes registers via I²C/SMBus/PMBus, and asserts ALERT on thresholds.

What it solves

Makes rails observable, actionable, and traceable—enabling efficiency profiling, protection triggers, and faster field diagnostics.

How to select (3 steps)

Choose common-mode range and ADC resolution/SPS to avoid saturation and capture events.
Match PGA gain + R_shunt to thermal drop and surge I²t limits.
Define window/hysteresis/latch per channel to reduce false trips.

Pitfalls

Wrong current polarity convention → negative readings.
Energy counter rollover not handled → period loss.
Too little averaging near thresholds → ALERT chattering.
No SMBus PEC/timeout or brownout recovery flow.

2) What is it | Definition & Boundaries

A Power Monitor with ADC integrates a sense front-end, ADC, digital averaging, power/energy math, register map, and threshold/ALERT, exposing rail telemetry via I²C/SMBus/PMBus for a protection + observability loop.

Out of Scope (Boundaries)

🚫 Rail power-up sequencing or multi-rail timing control.
🚫 Multi-rail power coordination and orchestration.
🚫 Remote-sense/compensation amplifiers for regulation loops.
🚫 Thermal management or temperature control controllers.

Placement & Usage

Select high-side or low-side sensing per application; verify common-mode range and ground bounce.
Place the device close to the shunt (R_shunt); keep S± matched in length and away from switch nodes and return trunks.
Connect upstream to MCU/FPGA management via I²C/SMBus/PMBus.

Scope and boundaries of ADC-based power monitors: inputs (S+/S−, VIN) on the left and outputs (I²C/SMBus/PMBus, ALERT) on the right; exclusions listed below — Scope & boundaries (3:2): central ADC power monitor block with inputs/outputs; exclusions shown with ban icons.

3) Working Principle | System Block Diagram

The full signal chain from the shunt to registers/ALERT: R_shunt → differential front-end (high-CMR) → PGA → ADC (ΣΔ / SAR) → digital filter/averaging → math for V/I/P/E. Protection runs in a parallel path via window thresholds, hysteresis, deglitch time, and optional latch, while the host reads a mapped register set over I²C/SMBus/PMBus.

Sensing chain

R_shunt with Kelvin pick-off; route S± away from switch nodes/return trunks.
Differential front-end tolerates high common-mode; verify input range vs. rail maxima.
PGA aligns ΔV to ADC’s optimal span; check step/overload behavior.
ADC (ΣΔ: high resolution with built-in digital filtering; SAR: higher SPS, add averaging).
Digital averaging and decimation feed stable V, I, then compute P = V×I and E = ΣP·Δt with a fixed time base.

Quantities & math

V [V], I [A], P [W] = V×I, E [J] = Σ P·Δt (Δt from the sampling tick).
Energy accumulator may be optional (dashed-box in figure); define width and rollover handling.
Use atomic read (shadow registers or read-lock) for multi-byte E to avoid torn reads.

Thresholds & ALERT

Upper/Lower windows with hysteresis; per-channel independence preferred.
Deglitch time t_deglitch and optional “time-over-limit” gate reduce border chatter.
Latch vs. non-latch semantics; define clear-on-read / write-1-to-clear policy consistently.

Bus & registers

Register map (subset): SHUNT_V, BUS_V, CURRENT, POWER, ENERGY_L/H, AVG_CTRL, LIMIT_HI/LO, HYST, DEGLITCH, ALERT_MASK, STATUS, CONV_TIME, MODE.

PEC (SMBus CRC-8) on transfers; handle clock stretching and timeout.
Define a brownout recovery sequence and default-value audit on power-up.

Timing relations

t_conv (conversion time), sampling rate SPS = 1 / t_conv.
N (averaging window or effective decimation).
t_deglitch for ALERT filtering.
End-to-end latency ≈ N·t_conv + t_deglitch (first-order estimate).

Block diagram from shunt to ADC, digital math for P/E, thresholds to ALERT and bus readout; top three timing bars for t_conv, averaging N, and deglitch — Visual flow: top = measurement chain (Rshunt → front-end → PGA → ADC → filter → P/E math); bottom = thresholds/hysteresis/deglitch → latch → ALERT; right branch = host bus.

Bring-up checklist (do-first items)

Zero-current offset → full-scale linearity → step-load capture → threshold trigger & deglitch → energy rollover.
Record (t_conv, N, t_deglitch) matrix and resulting latency; lock ALERT clear policy end-to-end.

4) Technical Breakdown | Seven Layers

A vertical, deep-dive decomposition of measurement, timing, thresholds, bus robustness, and calibration. Each layer summarizes Decision → Rules/Math → Risks → Validation, without crossing into sibling topics.

4.1 High-side vs Low-side (topology & common-mode)

Decision: common-mode range, ground bounce, drop budget, start-up over-voltage margin.
Rules: V_cm,max ≥ rail max + noise margin; evaluate low-side ground coupling.
Risks: start-up over-CM, reverse flow, ground-referenced noise injection.
Validate: power-on/off/surge waveforms; CM sweep; injected ground-bounce tests.

4.2 ADC & Averaging (ΣΔ vs SAR)

Decision: resolution, SPS, bandwidth, noise/ENOB, latency budget.
Rules: ENOB↑ ≈ 0.5·log₂N for white-noise averaging; ΣΔ: built-in digital filters; SAR: rely on external averaging/filters.
Risks: over-averaging → slow response; t_conv beats with F_sw; filter passband ripple.
Validate: step-load + swept-tone; correlate equivalent noise/bandwidth vs transient response.

4.3 R_shunt & Range (with PGA)

Decision: ΔV=I·R, full-scale drop ≤ 1–2%·V_rail, pulse energy I²·R·t, TCR, PGA gain.
Rules: pick R for SNR vs drop/heat; choose PGA so input sits in the ADC sweet spot.
Risks: short-pulse heating, TCR drift, PGA saturation or recovery delay.
Validate: thermal sim + IR; steady-state rise; linearity across FS.

4.4 Power/Energy Math (direction & rollover)

Decision: current sign convention (source/load or charge/discharge); accumulator width & read order.
Rules: unify sign across firmware; use shadow/locked reads; handle rollover explicitly.
Risks: sign flips causing P spikes; accounting gaps on rollover; Δt mismatch bias.
Validate: direction-switch test; long-horizon energy audit vs. bench reference.

4.5 Thresholds & ALERT (window/hysteresis/deglitch/persistence)

Decision: window widths, hysteresis, t_deglitch, time-over-limit, channel queue/priority.
Rules: hysteresis ≥ (3–5)×σ_noise; t_deglitch ≥ (1–2)× control-cycle jitter.
Risks: border chatter, uncleared latch, race conditions in cascaded protection.
Validate: boundary sweeps + jitter injection; ALERT clear & re-entry tests.

4.6 Bus Robustness (SMBus/I²C)

Decision: enable PEC; set timeout (SMBus ~35 ms typical); allow clock stretching; resolve address conflicts.
Rules: define brownout recovery; verify reset/default registers; re-probe + backoff.
Risks: bus lock, abnormal NACK, mis-reads/writes, multi-master collision.
Validate: fault injection/hot-plug; PEC error injection; large-batch address scans.

4.7 Calibration & Drift (zero/gain/temperature)

Decision: zero/gain models, temperature coefficients, factory record format, field re-cal flow.
Rules: short-zero, two-point (or multipoint) gain; build T vs correction; persist cal constants in NVM.
Risks: drift accumulation, lot variation, harness drop causing system-level bias.
Validate: chamber-based calibration; field quick-recal with known load/current source.

Seven-layer technical stack from sensing to calibration for ADC power monitors; risk badges on the right — Seven layers: topology → ADC & averaging → shunt & range → power/energy math → thresholds & ALERT → bus robustness → calibration & drift.

Validation summary (what to ship with the design review)

Topology choice memo (high-side/low-side) + CM/ground-bounce evidence.
ADC mode & averaging settings with ENOB vs latency plot; t_conv vs F_sw beat check.
R_shunt/PGA selection table (drop, heat, pulse I²t, TCR drift) and linearity sweep.
Threshold window/hysteresis/deglitch numbers; latch policy; ALERT queue/priority.
Bus robustness plan (PEC, timeouts, recovery); calibration record & field re-cal procedure.

5) Key Metrics | Field Definitions + Selection Hints

What to look at, why it matters, and how to verify on the bench. Desktop presents a compact table; a card grid below mirrors the same content for small screens.

Key metrics grid for selecting ADC-based power monitors and verification hints — Visual overview of selection metrics: common-mode, ADC resolution/SPS, gain & full-scale ΔV, offset/gain error, power/energy registers, ALERT behavior, and bus features.

Metric	Typical / Options	Why it matters	How to verify
Common-mode range	0–36 / 60 / 85 V (+ start-up transient margin)	Enables high-side sensing; survives inrush/surge and load disconnects.	Power-on/off/surge captures; CM sweep; confirm no saturation/lock-up.
ADC resolution / SPS	12–20 bit; ~10–2k+ SPS (t_conv vs N)	Sets ENOB and event capture bandwidth / latency trade-off.	Zero-input noise; ENOB vs SPS/N curve; step-load bandwidth test.
Gain & full-scale ΔV	±40–320 mV (with PGA settings)	Balances R_shunt SNR vs drop/heat; avoids PGA saturation.	2-point/linear sweep; overload recovery; step response around FS.
Offset / Gain error	Offset: µV; Gain: %FS (with temp drift)	Critical for standby/small current; long-term energy accuracy.	Zero-short + known load; thermal chamber drift characterization.
Power / Energy registers	24/32/48-bit; fixed Δt; explicit units/scaling	Defines audit window & rollover behavior; atomic read requirement.	Long-horizon audit vs meter; rollover + shadow/lock read tests.
ALERT behavior	Window, hysteresis, deglitch, latch/non-latch, queue/priority	Prevents border chatter; coordinates multi-rail protection.	Boundary sweep + jitter injection; time-over-limit & latch clear.
Bus features	SMBus timeout, PEC, clock stretching	Robust in hot-plug and large fleets; mitigates mis-reads/writes.	PEC error injection; timeout/stretch; multi-master/address conflicts.

Common-mode range

Typical/Options: 0–36 / 60 / 85 V (+ start-up margin)

Why: Enables high-side sensing; survives inrush/surge.

Verify: Power-on/off/surge captures; CM sweep.

ADC resolution / SPS

Typical/Options: 12–20 bit; ~10–2k+ SPS (t_conv vs N)

Why: ENOB vs bandwidth/latency trade-off.

Verify: Noise floor; ENOB vs SPS/N; step-load test.

Gain & full-scale ΔV

Typical/Options: ±40–320 mV with PGA

Why: R_shunt SNR vs drop/heat; avoid saturation.

Verify: Linearity sweep; overload recovery; step response.

Offset / Gain error

Typical/Options: Offset µV; Gain %FS

Why: Small/standby current accuracy; energy totals.

Verify: Zero-short; known load points; chamber drift.

Power / Energy registers

Typical/Options: 24/32/48-bit; fixed Δt; explicit units

Why: Audit window and rollover; atomic reads.

Verify: Long-horizon audit; rollover & shadow-read tests.

ALERT behavior

Typical/Options: Window, hysteresis, deglitch, latch, queue

Why: Stable triggers; multi-rail coordination.

Verify: Boundary sweep + jitter; time-over-limit & clear.

Bus features

Typical/Options: SMBus timeout, PEC, clock stretch

Why: Fleet-scale robustness; hot-plug safety.

Verify: PEC injection; timeout/stretch; multi-master tests.

6) Design Guidelines | Ten Executable Tips

Ten practitioner rules with Why → How → Verify, focused strictly on ADC power monitors.

Ten design rules for reliable ADC power monitoring implementation — Card grid: Rshunt, Kelvin routing, front-end RC, t_conv vs F_sw, averaging, sign convention, energy registers, bus robustness, thermal/mechanical, production test.

1) R_shunt selection

Why: Balance SNR vs drop/heat.

How: FS drop ≤ 1–2%·V_rail; check pulse I²·R·t & power rating; allow TCR headroom.

Verify: IR/thermocouple + pulse bench; long steady-state rise.

2) Kelvin routing

Why: Keep S± clean from return currents.

How: Equal-length S+/S−, avoid switch nodes/return trunks, maintain reference plane isolation.

Verify: Differential scope probing + current-path audit.

3) Front-end RC

Why: Suppress out-of-band noise/spikes without harming steps.

How: Start 10–100 Ω / 1–10 nF; pole < ADC BW; verify step fidelity.

Verify: Step-load and swept-sine response.

4) t_conv vs F_sw

Why: Avoid beating/aliasing.

How: Choose non-integer relationships; optionally dither t_conv (±3–7%).

Verify: Spectrum sidebands; event miss-rate audits.

5) Averaging strategy (N)

Why: Trade noise vs response.

How: Border-critical quantities: larger N + hysteresis/deglitch; transient-critical: small N.

Verify: ENOB-vs-N and step-response comparison.

6) Direction & sign

Why: Prevent control misjudgment when P and I disagree.

How: Unify source/load (or charge/discharge) sign across registers and host.

Verify: Four-quadrant scenarios and sign-flip tests.

7) Energy registers

Why: Reliable long-period accounting.

How: Note width & Δt; atomic reads (shadow/lock); rollover + daily/weekly closing.

Verify: Long-horizon audit and forced rollover tests.

8) Bus robustness

Why: Prevents bus hangs and data corruption in the field.

How: Enable SMBus timeout + PEC; re-probe on brownout; register reset script.

Verify: Hot-plug/cable faults, PEC injection, multi-master contention.

9) Thermal & mechanical

Why: Drift/failure from heat and vibration.

How: Keep R_shunt away from hot spots; prefer 4-terminal types; stronger pads/teardrops in vibration.

Verify: HALT/vibration + thermal cycling; drift statistics.

10) Production test consistency

Why: Traceability and cross-lot uniformity.

How: Establish V/I/T traceability; scripted sweeps; store cal constants & lot info in device records.

Verify: Cross-lot comparison and threshold regression.

Design takeaway

Lock common-mode headroom, size R_shunt + PGA for FS fidelity, choose ADC mode & N for latency/ENOB, harden ALERT semantics, and enforce PEC/timeout with a repeatable calibration + audit flow.

7) Layout & EMI | PCB Guidelines

Prevent measurement errors and ALERT chatter by partitioning the power and sensing domains, routing S± as a clean Kelvin pair, and hardening the bus and interrupt lines.

Placement & Partition

Separate R_shunt + S±, ADC front-end, and power switching zone.
Draw a grounded “moat” between high-dv/dt nodes and the sensing island.
Mark the SW-node vicinity as a no-go shadow for S± traces.

Routing (S±)

Kelvin pick-off; S± tightly coupled, equal length, minimal vias.
Keep away from switch nodes, fast current returns, and slot cuts.
Place the RC input filter close to the monitor pins.

Grounding & Return

Join AGND ↔ PGND at a single point; avoid sensing return crossing power return.
Use via fences/guard traces where S± transition layers or pass noisy zones.

Front-end Filtering & Anti-alias

Start with 10–100 Ω / 1–10 nF; set pole below ADC bandwidth.
Size ALERT pull-up by bus fan-out/capacitance; add small RC deglitch if needed.

I²C/SMBus Integrity

Estimate line C and pick pull-ups for compliant edges; allow clock stretching.
Enable PEC; place ESD near the connector; consider series damping for long runs.

Layout and EMI best practices: top-view PCB with highlighted Rshunt, S± Kelvin routing, RC near ADC, ALERT pull-up, I²C, AGND/PGND and SW-node no-go shadow — Object-only layout map with concise labels: Rshunt, S+, S−, ADC front-end, RC, ALERT, I²C, AGND/PGND, SW no-go zone.

Kelvin S±; keep a continuous reference plane below the pair.
Place RC at the monitor pins; verify step fidelity vs noise.
Single-point AGND–PGND tie with clear return planning.

Don’t

Don’t cross S± over the SW node or split planes/slots.
Don’t share S− return with high di/dt loops.
Don’t oversize bus pull-ups; avoid ringing/slow edges.

Validation checklist

Near-field probe and step-load sweep before/after RC and routing changes.
Zero-current drift vs temperature with AGND/PGND tie variations.
ALERT chatter statistics under boundary sweeps and injected jitter.
I²C edges, timeout, stretching and PEC error-injection report.

8) Register & Data Model | Minimal Closed Loop

A minimal, production-ready register set grouped as CONFIG, MEASURE, STATUS, and SERVICE, plus a power-on→run→interrupt→recovery→settlement flow.

CONFIG

MODE, CONV_TIME, AVG/N, PGA.
THRESH_HI/LO (V/I/P), HYST, DEGLITCH, PERSIST.

MEASURE

BUS_V, SHUNT_V, CURRENT, POWER.
ENERGY_L/H, TIMEBASE, direction bit (source/load or charge/discharge).

STATUS

ALERT_STATUS, ALERT_MASK, FAULT_LOG[n] (timestamp + reason).
Optional ROLL_CNT for energy rollover accounting.

SERVICE

DEVICE_ID, REV, RESET.
Telemetry health: PEC_ERR_CNT, TIMEOUT_CNT.

Power-on → Configure

Read DEVICE_ID/REV & issue RESET.
Write MODE, CONV_TIME, AVG, PGA.
Program THRESH_HI/LO, HYST, DEGLITCH, PERSIST; clear ALERT_STATUS.

Run → Interrupt → Recovery → Settlement

Periodic shadow/locked reads of MEASURE; compute P/E; log.
On ALERT#: read ALERT_STATUS/FAULT_LOG → act → clear (W1C/read-to-clear aligned).
If TIMEOUT_CNT or PEC_ERR_CNT grows: bus reset, re-probe, re-apply CONFIG.
Periodic settlement: read ENERGY_L/H (+ optional ROLL_CNT) and archive.

Consistency & precision

Atomic energy reads via shadow/lock; verify no torn updates across L/H words.
Publish unit scales (μV/LSB, mA/LSB, mW/LSB, mJ/LSB) and a versioned TIMEBASE.
Unify current/power sign convention across registers and host calculations.
FAULT_LOG stores type, thresholds, persistence duration, and timestamp.

9) Firmware Patterns | ISR & Polling Flow

A vendor-agnostic organization pattern for power monitors with ADC: a non-blocking main loop, a minimal ISR, a single-producer/single-consumer event queue, and deterministic settlement tasks.

Monotonic Time Base & Data Path

Single monotonic clock drives t_conv, averaging N, deglitch t_deglitch, and settlement cadence.
Main Loop (non-blocking): shadow/locked reads → scale/smooth → energy accumulate (E += P·Δt).
ISR (ALERT): capture minimal set (status + offending regs), timestamp, push to ring buffer. No blocking I²C

Polling Mode (optional)

Beat schedule avoids integer relationships with F_sw; jitter if necessary.
Choose N: boundary decisions → larger N; event capture → smaller N.
Secondary firmware thresholds (window/hysteresis/persist) reduce chatter.

Interrupt Mode (recommended)

On ALERT#: ISR snapshots ALERT_STATUS + related channel → enqueue (ts, type, rail, persist ticks).
Worker task performs deglitch/persist confirmation; logs to FAULT_LOG and triggers protection/UI.
Prioritize PG/protection events > statistics to avoid queue starvation.

Exception Recovery

If PEC_ERR_CNT/TIMEOUT_CNT exceeds threshold: bus reset → re-probe address → re-apply CONFIG (idempotent).
Power-loss resume: verify DEVICE_ID/REV, clear status, re-align TIMEBASE.

Settlement & Archiving

Daily/weekly energy roll-up (read ENERGY_L/H + ROLL_CNT), persist peak I_pk/P_pk.
Optional signing/hash for evidence chain with TIMEBASE & coefficient version.

Two swimlanes: Main Loop and ISR. ISR snapshots on ALERT, pushes to Event Q. Worker confirms, logs, and acts. Note: No blocking I²C in ISR. — Object-only firmware flow: Main Loop, ISR, Event Q, Worker; with **No blocking I²C** warning.

Minimal Event Queue Contract

Single producer (ISR) / single consumer (worker) ring buffer; fixed length; overwrite policy keeps latest and increments drop_cnt.
Payload: ts_ms, rail_id, type, persist_ticks, status_bits.

10) Calibration & Validation | Traceable Accuracy

A reproducible, traceable workflow covering factory coefficients, field quick-check, environmental validation, energy rollover tests, and documentation for audits.

Factory Calibration

Offset (open/short loop); Gain (0, I_mid, I_max); Temp drift (two-point).
TIMEBASE ppm vs reference clock; version the scale/units.
Persist coeffs/date/fixtureID/firmwareREV/CRC to info area; printable certificate.

Field Quick Re-Trim

Known load or current source for two-point check; step method for linearity.
Two-temperature correction or LUT update from temp_coeff.
A/B before/after report: bias, gain, repeatability.

Validation Scripts

Sweep: I: 0→Imax→0, N samples/point; record V/P/E synchronously.
Thermal: −20→85 °C; extract offset(T), gain(T); check limits.
Linearity/Repeatability thresholds; Energy rollover with ROLL_CNT.
ALERT boundary sweeps (PERSIST/DEGLITCH combos); bus PEC/timeouts injection tests.

Documentation & Traceability

Log: coefficients, TIMEBASE, ROLL_CNT, PEC_ERR_CNT, operator/location/fixtureID, firmware REV.
Version mapping for coeff tables and rollback path; optional signature/hash.

Three-block flow: Factory calibration (Offset, Gain, Temp, Timebase) → Field quick re-trim → Periodic review; outputs: Coeff Card and Record Card for traceability. — Factory → Field → Periodic flows with concise object labels only; certificate and record cards at the output.

Acceptance (examples)

Zero-offset ≤ X μA @25 °C, drift ≤ Y μA/°C.
Gain error ≤ Z %FS across temperature.
Repeatability ≤ R % (10 repeats/point).
Energy deviation ≤ E % vs external meter.

Minimal Fixture & Environment

Programmable PSU + e-load + DMM (SMU ideal), optional thermal chamber.
Four-wire Kelvin connections; short, shielded leads; robust Kelvin clips.

11) Accuracy Budget | Error Sources & RSS

A fast, traceable way to estimate uncertainty for I, P, and E with ADC-based power monitors: map contributors, combine with RSS, and validate with minimal scripts.

Error Sources (object level)

PGA gain error (ε_gain) and offset V_off.
Quant/Noise (ENOB, LSB/√12, averaging N), INL/DNL.
R_sh TCR & self-heating (I²R·θ_JA), lead mismatch (non-Kelvin).
Bandwidth/anti-alias deficit (k_BW), temp drift of gain/offset.

Quick Equations (first-order)

Current estimate: Î = ΔV_sh / (A_PGA·R_sh).
Offset to current: ΔI_off ≈ V_off / (A_PGA·R_sh).
Quantization σ: σ_q ≈ (LSB/√12)/√N → σ_I,q = σ_q / (A_PGA·R_sh).
TCR term: ΔR/R ≈ TCR·ΔT ⇒ scales I, P, E.
RSS combine (current): u_I ≈ √[(ε_gain·I)² + ΔI_off² + σ_I,q² + (ε_INL·I)² + (TCR·ΔT·I)² + ΔI_lead²].
Power: u_P ≈ √[(I·u_V)² + (V·u_I)²]; Energy: timebase + power uncertainty.

Typical Scenarios (dominant terms)

A — Standby (5 mA)

Offset / Quant dominate; raise N, lengthen t_conv.

B — Mid-load (2 A)

Gain & TCR dominate; factory gain trim + TCR model.

C — High current (20 A)

Self-heating (ΔT) + lead mismatch; enforce Kelvin.

D — Ripple/Edge

k_BW deficit; verify step fidelity / anti-alias.

E — High temp

Gain/offset drift; two-point temp correction.

Error sources tree feeding an RSS box, output as total error bars for I, P, E. Object-only labels: Gain, Offset, Quant/Noise, INL, TCR, Leads, BW, Drift, RSS Combine, Total Error Bars. — Object-only diagram: **Error Sources → RSS Combine → Total Error Bars** (I / P / E).

Mitigations

Increase t_conv and N; avoid integer beats with F_sw.
Front-end RC & anti-alias; confirm step fidelity.
Factory + field calibration; LUT for TCR/drift.
Wider hysteresis + deglitch for boundary decisions.
Strict Kelvin routing; symmetric leads.

How to Verify

Offset/Noise: short loop + long sampling stats.
Gain/Linearity: multi-point current steps; fit + residuals.
TCR/Drift: two-temp or chamber run; log ΔR and gain/offset drift.
Bandwidth: step & frequency sweep → k_BW factor.
Timebase: ppm vs reference clock.

12) Production Test | Flow & Traceability

Integrate power-monitor capability into the mass-production quality loop: fixture, flow, thresholds regression, energy rollover test, bus robustness, and complete data capture.

Fixture & Equipment (minimal)

Four-wire Kelvin to R_sh; programmable PSU + e-load/SMU; precision DMM.
Sense MUX (optional), thermal chamber (optional, sampling).
I²C/SMBus adapter with PEC/timeout/stretch support; ESD protection; cable discipline.
Golden board/device for daily drift check.

Test Flow (lane view)

Per-rail sweep 0→I_mid→I_max; log V/I/P.
Write offset/gain/temp coeffs; version the info area.
Threshold regression: window/hysteresis/persist/latched behavior.
Energy rollover: force overflow (timebase or width) and verify ROLL_CNT + daily/weekly settlement.
Bus robustness: PEC faults/timeout injection; verify recovery script (reset → re-probe → restore CONFIG).
Archive to MES/DB; print label or QR.

Data Fields (traceability)

SN, board#, lot, line, operator, fixture ID, FW rev.

Env

Temp, RH, supply, cable/clip IDs.

Coeff

offset, gain, temp_coeff, timebase_ppm, scale_ver.

Stats

PEC_ERR_CNT, TIMEOUT_CNT, ROLL_CNT, ALERT_tests_pass.

Result

points, R², repeatability, disposition.

Signature

hash/signature + timestamp (optional).

Throughput & Takt

Per-channel flow ≤ 60–90 s (no chamber).
Daily golden check ≤ 10 min; drift out-of-control triggers maintenance.

Production swimlanes: Fixture → DUT → Tester → DB, with steps Scan, Write Coeff, Alarm Test, Rollover, Robustness, Archive; right-side cards list traceability fields (ID, Env, Coeff, Stats, Result, Signature). — Object-only production test & traceability diagram for mass-production quality loop.

Exception Library (for rework orders)

Offset out-of-limit / Gain out-of-limit / ALERT behavior mismatch / Rollover abnormal / Bus robustness fail / Minor drift.
Each exception maps to a Fail Code → Rework Order with cause, action, and retest requirements.
Link each SN to its black-box record in the quality page.

13) Troubleshooting Matrix | Symptom → Fields → Cause → Fix

A minimal closed loop for first-line diagnosis. Map the symptom to observable fields, identify the likely cause, then apply the corrective action.

Small current unstable

Fields: I/P jitter

Cause: Offset / Quantization / Ripple

Fix: Increase t_conv & N; optimize RC.

Reading negative

Fields: I < 0

Cause: Polarity map mismatch / S± swapped

Fix: Unify sign convention; rewire S±.

ALERT storm

Fields: ALERT_STATUS floods

Cause: Hysteresis / Persist too low

Fix: Add hysteresis, deglitch, larger N.

Near-FS clipping

Fields: Samples at FS

Cause: Rshunt too high or PGA too high

Fix: Lower gain or choose smaller Rshunt.

Energy jump

Fields: E step / ROLL

Cause: Rollover unhandled or Δt wrong

Fix: Implement rollover & unified timebase.

Bus lock

Fields: Timeout / Hold

Cause: Clock stretching or noise

Fix: Enable SMBus timeout + PEC; add recovery script.

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14) Applications & Reference Circuits (Brand-agnostic)

Four minimal yet sufficient templates that cover the most common field patterns. Each tile: one small circuit and 5–7 bullet points, with verification tips.

Four application tiles: A High-Side + Energy (Shunt → PGA/ADC → Bus + Energy Acc); B Dual Channel (CH1 Core, CH2 Periph → PGA/ADC → Bus + Shared ALERT); C Low-Side, Low-Voltage (Low-Side Shunt, Kelvin, RC, Bus); D High-Voltage 24–60 V (HV 60V, PGA/ADC, Bus, RC Clamp, Surge). — Object-only templates A–D: high-side+energy, dual-channel shared ALERT, low-side low-voltage, and 24–60 V high-voltage rail.

A — Single High-Side + Energy

High-side shunt, wide common-mode front-end.
t_conv chosen non-integer vs F_sw; N=16–64.
I/P windows with hysteresis; latched optional.
Energy accumulator with daily/weekly settlement.
Verify: step load + long-run energy audit.

B — Dual Channel: Core + Peripherals (Shared ALERT)

Per-channel PGA/FS; shared TIMEBASE.
Independent thresholds/deglitch per channel.
Shared ALERT with queue; priority documented.
Verify: cross-channel ordering & queue saturation.

C — Low-Side on Low-Voltage Rail

Minimal drop; high PGA; moderate N to avoid jitter.
Strict Kelvin sense; slit ground guard if needed.
Verify: ground-bounce injection & false-alert rate.

D — High-Voltage Rail (24–60 V)

Wide common-mode input; RC set; surge margin.
Cold-start transient tolerance; startup delay.
Persist and hysteresis balanced for compliance.
Verify: surge pulse + cold-start; check logs.

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15) Reference ICs & BOM Hints (examples only)

A landing pad for selection: grouped by need — High-resolution + Energy, Wide common-mode + Multi-channel, Fast response + Event capture. Part numbers are examples; before publishing you can swap to your in-stock/advantaged SKUs and link to your Ersa/Ampheo inquiry page. No cross-topic content.

BOM checklist quadrants with concise labels: Shunt (4-Terminal, Low TCR, I²t/Pulse Power, Kelvin Pads), RC (R 33–100 Ω, C 1–10 nF, C0G low drift, V rating ≥ 1.5–2×), Pull-ups (10 kΩ, 4.7 kΩ, Rise time spec, ALERT RC), Connectors (PMBus/I²C header, Coax test port, Kelvin test pads). — Object-only diagram for BOM hints — clean labels, brand-agnostic.

A) High-Resolution + Energy Accumulator

Use when: metering, efficiency profiling, long-period energy settlement.
Why: ΔΣ + programmable averaging → low noise; on-chip P/E/TIMEBASE.
Edges: ΔΣ bandwidth; energy width & rollover policy.

Example ICs

TI INA228 (I²C, 20-bit ΔΣ, P/E regs)
TI INA229 (SPI, 20-bit ΔΣ)
ADI LTC2947 (energy metering)
Microchip PAC1934 (I²C, 4-ch accumulators)

B) Wide Common-Mode + Multi-Channel

Use when: 24–60 V buses; board multi-rails with shared ALERT.
Why: consolidated cost; centralized interrupt & queue.
Edges: channel interleave; CM/surge margin at cold-start.

Example ICs

TI INA3221 (I²C, 3-ch)
Microchip PAC1934 (I²C, 4-ch)
ADI LTC2992 (I²C, dual-rail)

C) Fast Response + Event Capture

Use when: boundary enforcement; narrow spikes; ISR-driven alerts.
Why: shorter t_conv; deglitch & PERSIST tuned for events.
Edges: noise vs SPS trade-off; non-blocking I²C in ISR.

Example ICs

TI INA238 (I²C, higher SPS)
ADI LTC2946 (I²C, rich event regs)
Renesas ISL28022/28030 (I²C, robust ranges)

1) Shunt Resistor (prefer 4-terminal / metal alloy / low TCR)

Target: low drift, low thermal EMF, robust pads

Stackpole CSS2H-2512R-L100F — 0.01 Ω, 2512, 1%

Good wattage for 1–5 A ranges; cost-effective.
Metal alloy & large pads → better thermal handling.
Check: full-load drop ≤ 1–2% V_rail, I²t surge.

Bourns CSS2H-3920R-L050F — 0.005 Ω, 3920, 1%

Higher pulse energy reserve; lower drop at same I.
Wide body improves vibration robustness.
Check: layout clearance & Kelvin routing.

Susumu KRL3264E-M-R002-F — 0.002 Ω, 3264, 1%

Thin-film precision; low TCR for standby/current sense.
Good for low-drop high-current rails.
Check: power derating vs ambient.

Vishay WSLP2726-R001-F — 0.001 Ω, 2726, 1%

Ultra-low value → minimal budgeted drop.
High current with large footprint heat spreading.
Check: measurement resolution with chosen PGA.

2) Front-End RC (anti-alias / input shaping)

Start: 33–100 Ω + 1–10 nF; pole below ADC BW

KEMET C0603C102J5GACTU — 1 nF, 50 V, C0G, 0603

Low drift dielectric; stable transfer function.
Check: place near S±; Kelvin first.

KEMET C0603C332J5GACTU — 3.3 nF, 50 V, C0G

Stronger anti-alias; watch step fidelity.
Check: validate transient reproduction.

KEMET C0603C104K5RACTU — 0.1 µF, 50 V, X7R

Local decoupling for monitor VDD.
Check: bias derating of X7R.

Yageo RC0603FR-0733RL — 33 Ω, 0603

Series input damping; sets RC pole.
Check: not too high to distort step.

Yageo RC0603FR-07100RL — 100 Ω, 0603

Higher damping option for noisy rails.
Check: ADC BW & ENOB impact.

3) Bus / ALERT Pull-Ups

R ≈ t_r,max / (0.8473·C_bus) • I_OL ≤ spec

Yageo RC0402FR-0710KL — 10 kΩ, 0402

Short runs, low C_bus.
Check: pad strength vs rework cycles.

Yageo RC0603FR-0710KL — 10 kΩ, 0603

General default; robust footprint.
Check: rise-time to spec at target data rate.

Yageo RC0603FR-074K7L — 4.7 kΩ, 0603

For larger C_bus or 200 kHz.
Check: I_OL margin on all devices.

Yageo RC0603FR-072K2L — 2.2 kΩ, 0603

Long runs, heavier loading.
Check: bus sink capability & heating.

Tip: keep ALERT pull-up separate from SCL/SDA; add 1–4.7 nF RC on ALERT if boundary jitter is observed.

4) Connectors / Test Points (serviceability & traceability)

Shortest loops; away from switch nodes; shield when needed

Hirose U.FL-R-SMT-1(10) — micro coax port

Shielded probing for noise/spectrum capture.
Check: mechanical strain relief.

JST GH BM06B-GHS-TBT + GHR-06V-S — 6-pin service header

PMBus/I²C field maintenance port.
Check: include a ground pin & shielding.

Keystone 5015/5016 — SMD loop test points

Clamp-friendly Kelvin access for scopes.
Check: spacing vs high-voltage rails.

Selection Flow

Rail voltage/common-mode (incl. cold-start surge) → pick family.
Resolution vs bandwidth (ΔΣ vs SAR; N & t_conv).
Channels & queueing (shared ALERT vs per-channel).
On-chip energy/timebase/rollover needs.
Bus robustness (PEC/timeout/clock-stretching).
Register model vs your minimal usable set (see Section 8).

Verification Hooks

Metering: 0→I_mid→I_max→0 fit + residuals; 2-point temp.
Events: pulse-width sweep; PERSIST, hysteresis, deglitch matrix.
Roll/Δt: force energy rollover; record TIMEBASE ppm drift.
Production: write coeff → threshold regression → roll → PEC/timeout injection → archive.

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16) FAQ — Power Monitors with ADC

Below are the most asked, conversion-oriented questions. Answers are concise (≈40–70 words), brand-agnostic, and match the front-end copy exactly. Use the anchors to deep-link from other sections. This chapter intentionally contains no JSON-LD output here.

How do I choose Rshunt and PGA for tiny standby currents?

Pick Rshunt so ΔV at the highest expected standby current reaches 30–60% of the PGA full-scale, while full-load drop stays within 0.5–2% of V_rail. Prefer 4-terminal, low-TCR parts. Map PGA so noise-free counts cover standby. Verify with zero-short, known precision load, and temperature sweep to validate offset and drift.

How should t_conv and digital averaging avoid beating with the switch frequency?

Avoid integer multiples between conversion time and F_SW. Choose prime-like ratios or slightly dither t_conv if available. Keep averaging window N moderate for events, larger for stability. Validate with step-load and a spectral view: no stationary ripples in the sampled sequence and no recurring threshold crossings from aliasing.

What initial values are safe for window thresholds, hysteresis, and deglitch?

Start with window limits at ±5–10% around the nominal metric or 5–8× RMS noise, whichever is larger. Set hysteresis to 3–5× RMS noise or 0.5–1% FS. Use deglitch/persist of 2–4 samples. Tune per rail: increase for noisy domains, decrease where fast protection outweighs nuisance-trip risk.

How do I prevent data loss when the energy counter rolls over?

Use atomic reads (shadow/lock registers if available), track a rollover counter, and compute energy with modular arithmetic on a documented timebase. Periodically settle daily/weekly totals to non-volatile storage. In logs, record E width, Δt, and rollover count so analytics can reconcile long-horizon energy accurately.

When should ALERT be latched versus non-latched?

Use latched ALERT for safety-critical or compliance conditions that must be acknowledged (e.g., sustained over-current). Use non-latched for telemetry thresholds and soft margins to reduce service load. Always pair with hysteresis and deglitch/persist, and document the clear path and queue priority.

What should I do if the PEC error counter rises?

Treat rising PEC as a bus-health signal. First, lower bus speed and check pull-ups versus C_bus. Inspect routing, stubs, and cable length. Enable SMBus timeout and implement a soft-reset + re-enumeration routine. Log device address, attempt counts, and PEC bursts to isolate noisy segments or marginal connectors.

What is the fastest practical field re-calibration flow?

Warm to operating temperature, run a zero-short to capture offset, then apply a traceable load point near typical current for gain. If possible, repeat at a second temperature for a two-point temp fix. Store coefficients, date, rig ID, and firmware version. Re-verify with a step-load and record residuals.

How do ΣΔ and SAR ADCs trade off in V/I/P monitoring?

ΣΔ offers higher ENOB and better rejection with configurable averaging but lower bandwidth—ideal for metering and stable rails. SAR reaches higher SPS and lower latency—better for event capture and fast limits. Pick per rail: metering → ΣΔ; boundary enforcement or narrow spikes → SAR or ΣΔ with minimal averaging.

What are layout pitfalls for high-side versus low-side sensing?

For high-side, keep S+/S− Kelvin short and away from switch nodes; ensure CM range and startup transients are within ratings. For low-side, prevent ground return currents from crossing the sense leads; use a single-point tie to power ground. In both cases, add a small RC and maintain a quiet reference.

How do I keep “peak I/P snapshots” consistent between production test and field logs?

Use the same timebase, averaging, and ALERT/deglitch settings as production. Capture peaks in an ISR or timestamped queue to avoid bus blocking. Include firmware build, coeff version, and N/t_conv in the record. Validate with scripted step profiles that reproduce production-line maxima.

How do I avoid ground bounce on low-voltage rails with low-side sensing?

Create a star ground so high load currents do not pass through the sense reference. Place Kelvin returns directly at the shunt pads, add minimal RC to tame high-frequency content, and keep loop area small. Verify by injecting load steps and confirming the sensed voltage does not mirror switching-ground movement.

When do I need a multi-channel monitor instead of multiple chips?

Choose multi-channel when you need shared ALERT/queueing, a synchronized timebase, and lower BOM/area for correlated rails. Prefer multiple chips when you require isolation, distinct common-mode ranges, separate addresses/buses, or when physical placement near each rail shortens Kelvin paths and improves measurement fidelity across the board.

Power Monitors with ADC: Shunt Sensing, ADC, Bus Telemetry, ALERT

Quick Browse

1) Answer Box | Decision Snapshot

2) What is it | Definition & Boundaries

3) Working Principle | System Block Diagram

4) Technical Breakdown | Seven Layers

5) Key Metrics | Field Definitions + Selection Hints

6) Design Guidelines | Ten Executable Tips

7) Layout & EMI | PCB Guidelines

8) Register & Data Model | Minimal Closed Loop

9) Firmware Patterns | ISR & Polling Flow

10) Calibration & Validation | Traceable Accuracy

11) Accuracy Budget | Error Sources & RSS

12) Production Test | Flow & Traceability

13) Troubleshooting Matrix | Symptom → Fields → Cause → Fix

14) Applications & Reference Circuits (Brand-agnostic)

15) Reference ICs & BOM Hints (examples only)

16) FAQ — Power Monitors with ADC

Related Articles

Power Monitors with ADC: Shunt Sensing, ADC, Bus Telemetry, ALERT

Quick Browse

1) Answer Box | Decision Snapshot

2) What is it | Definition & Boundaries

3) Working Principle | System Block Diagram

4) Technical Breakdown | Seven Layers

5) Key Metrics | Field Definitions + Selection Hints

6) Design Guidelines | Ten Executable Tips

7) Layout & EMI | PCB Guidelines

8) Register & Data Model | Minimal Closed Loop

9) Firmware Patterns | ISR & Polling Flow

10) Calibration & Validation | Traceable Accuracy

11) Accuracy Budget | Error Sources & RSS

12) Production Test | Flow & Traceability

13) Troubleshooting Matrix | Symptom → Fields → Cause → Fix

14) Applications & Reference Circuits (Brand-agnostic)

15) Reference ICs & BOM Hints (examples only)

16) FAQ — Power Monitors with ADC

Related Articles

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