Voltage Comparator: Basics, Hysteresis, Selection

A voltage comparator compares two input voltages and drives a binary output for threshold/window detection, edge timing, and front-end protection. This hub is intent-first: overdrive vs propagation-delay, outputs & pull-ups, hysteresis, CMVR/clamps, window planning, interfacing, validation, application playbooks, selection matrix, BOM and FAQs—so readers can progress from “understand” to “select & procure”.

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1 What & When 2 Overdrive vs Delay 3 Outputs & Pull-Up 4 Hysteresis 5 CMVR & Clamp 6 Window Comparator 7 Interfacing 8 Validation 9 Patterns & Previews 10 Applications 11 Selection Matrix 12 BOM & Procurement 13 FAQs

What & When

A voltage comparator is an analog decision device that compares two input voltages and drives a binary output. Used in threshold and window detection, timing edges, and front-end protection, a voltage comparator IC asserts when the non-inverting input exceeds the inverting input and de-asserts otherwise.

How it works

Two inputs (V+, V−) and one digital-style output (Vo).
Huge open-loop gain turns tiny ΔVIN into rail switching.
Propagation delay shrinks with larger overdrive and faster devices.
Add positive feedback (hysteresis) to stop chatter near threshold.

Key features & applications

Open-loop switching (not linear op-amp feedback).
Threshold detection using fixed or divided Vref.
Building block for window checks and ADC timing edges.
Hysteresis to suppress ripple-induced toggling on slow ramps.

Voltage comparator IC with V+, V−, Vref and binary output Vo on a deep blue background — Binary output asserts when V+ exceeds V−.

Trip Logic

If V+ > V− → Vo = HIGH; otherwise LOW. Inverting topology flips the sense.

Speed vs Overdrive

Propagation delay TPD decreases as input overdrive ΔVIN increases; at tiny overdrive expect about 1.2–1.5× nominal TPD.

Noise Hardening

V_hys ≥ 3× V_in,pp (≥ 4× for automotive) to suppress ripple-induced chatter; large source impedance can dilute hysteresis—buffer or reduce source R.

CMVR Reality

Near the rails the valid input common-mode range can shrink and TPD can worsen. Verify RRIO/CMVR and re-measure timing at corner conditions.

Jump to interface choices · see delay vs overdrive

Overdrive vs Propagation Delay

Goal: Given shortest pulse width and ΔVIN, decide if pulses will be missed.

ΔVIN < 5 mV → TPD ≈ 1.2–1.5× nominal (near-threshold slows switching).
ΔVIN ≥ 100 mV → approaches device minimum TPD.
Sweep ΔVIN × Temperature × VDD; record minimum and worst-case TPD.
If 2 × TPD ≥ τ_min (shortest pulse), use a faster device or increase ΔVIN.

Practical Bound

For single-shot capture, require pulse_min ≥ 3 × TPD_max to absorb asymmetry and output filter.

Cold-Corner Risk

Cold often lengthens TPD 10–30%. Validate with small ΔVIN at −40 °C (or device minimum).

Jitter Budget

Comparator adds edge uncertainty ≈ σ_T ≈ σ_noise / (dV/dt) at threshold. Increase slew or hysteresis.

Propagation delay vs input overdrive ΔVIN with tiny, typical and large regions; narrow-pulse loss shaded — Delay falls as overdrive grows; tiny-ΔVIN risks missing narrow pulses.

Detect tiny-ΔVIN pulses →

Outputs & Pull-Up Choices (OD/PP)

Goal: Choose open-drain vs push-pull; size pull-up so rise time does not clip the shortest pulse.

Open-drain: easy level mixing and wired-AND; rise time set by R_PU × C_L.
Push-pull: symmetric edges for higher speeds; ensure level-domain compatibility.
Rule of thumb: t_r ≈ 2.2 · R_PU · C_L; require t_r ≤ 0.1 · τ_min.
Back-solve R_PU,max and current I ≈ V_PU/R_PU; for multi-sources ensure ΣI_sink ≤ I_OL(max).

Sizing Shortcut

Given τ_min and C_L, set R_PU ≤ 0.045 · τ_min / C_L (uses 0.1× rule with 2.2 factor).

Cross-Domain Pull-up

When level-shifting, pull-up to the receiving domain; confirm absolute max on the comparator’s output.

Wired-AND Budget

For N sinks, ensure N · I_leak + I_pullup(HIGH) ≤ I_OH of the receiving gate; check low-level VOL at I_OL.

Open-drain comparator with pull-up resistor and load capacitance; rise time set by R × CL — Pull-up and load set rise time; keep it well below the shortest pulse.

See pull-up sizing →

Hysteresis for Noise Immunity

Goal: Choose “enough” hysteresis for ripple/slow-ramp rails and avoid chatter.

Baseline: V_hys ≥ 3 × V_in,pp; automotive: ≥ 4 ×.
Large source impedance reduces effective hysteresis; buffer or lower the source resistance.
Sampling window must cover typical ripple, not rare spikes.
Asymmetric thresholds can dodge ripple peaks/valleys.

Design Formula

For inverting Schmitt: V_hys ≈ V_OUT,pp · R1/(R1+R2). Tune by the feedback ratio; keep bias currents in budget.

Slew-Rate Link

Edge stability needs V_hys > σ_noise · 6 and dV/dt high enough that σ_T ≪ τ_min/10.

Sensor Front-Ends

For slow sensors (NTC, shunts) place RC pre-filter before comparator; set f_c below ripple, above event bandwidth.

Comparator with hysteresis (Schmitt trigger) showing dual thresholds rejecting ripple noise — Dual thresholds (VTH+ / VTH−) reject ripple around the trip point.

Hysteresis formulas & 10 cases →

CMVR, Input Protection & Clamp

Goal: Keep inputs safe and valid near rails and during over-voltage events.

Near rails, confirm input common-mode range (CMVR) or RRIO tolerance.
When ESD/clamp diodes conduct, limit I_clamp ≤ 1 mA via series resistance.
For ±12 V, +48 V, or ISO 7637-2 transients, combine series R with TVS/RC.
Small ΔVIN near CMVR edges can lengthen TPD — re-measure at corners.

±12 V Input

Series R ≈ 12–22 kΩ; add small RC (e.g., 1–4.7 nF) to tame spikes.

+48 V Lines

Series R ≈ 47–100 kΩ plus SMBJ class TVS; check input leakage/headroom.

Automotive Surge

Series R + 600–1000 W TVS; validate under ISO 7637-2/ISO 16750 pulses.

High-voltage input protection for low-voltage comparators; clamp current kept below 1 mA — Keep clamp current small and verify CMVR near rail limits.

High-voltage inputs — clamp & CMVR →

Window Comparator (Two Comparators)

Goal: Detect “in-range / out-of-range” and budget threshold errors.

Two comparators plus a divider define VTH_L and VTH_H.
Error stack (approx.): σ ≈ √(Vref%² + Rdiv%² + VOS%²); add temperature drift linearly.
Open-drain OR outputs share one pull-up; expect asymmetric delays.
Supervision parts with internal reference/hysteresis reduce drift and PCB spread.

Tolerance Budget

Treat divider tolerance as RSS with reference and offset; for tight windows use 0.1% resistors and low-drift ref.

Delay Asymmetry

With open-drain, LH and HL paths differ (passive pull-up). Check both against minimum pulse width.

Noise Margin

Set VTH_H − VTH_L > worst-case ripple + offsets + temp drift to avoid window flapping.

Window comparator with upper and lower thresholds and stacked error contributors — Upper/lower thresholds define the pass band; track reference and divider errors.

Window error budget details →

Interfacing

Connect comparators to downstream logic with clear rules for current budgeting, rise/fall shaping, and level-domain matching. Focus on wired-AND behavior, pull-up placement, and module board caveats (LED + large pull-ups).

Wired-AND comparators sharing one pull-up; pull-up in receiving domain; series damping at driver — Pull up to the receiving domain; check ΣI_sink and use a 33–100 Ω series resistor near the driver.

Wired-AND Budget

For N sources sharing one pull-up: ΣI_sink ≤ I_OL(max) of the active comparator. Estimate I_sink ≈ Σ[(VPU−VOL)/R_PU,i] + ΣI_leak,i.

Rise-Time Bound

Use t_r ≈ 2.2·R_PU·C_L and require t_r ≤ 0.1·τ_min to avoid pulse clipping.

Level Domain Choice

Pull up to the receiving domain (MCU/FPGA). Check output absolute max and VIH/VIL windows.

Series Damping

Place a 33–100 Ω series resistor near the driver to tame ringing/EMI on cables/backplanes.

Worked Example — 3.3 V bus, N=3 sources

Given R_PU=4.7 kΩ, C_L=50 pF, target τ_min=20 ns. Rise time t_r≈2.2·4.7k·50p≈517 ns → fails. Need R_PU ≤ 0.045·τ_min/C_L ≈ 18 Ω (use 100–330 Ω practical + driver sink check), or reduce C_L/buffer the node.

Module wiring note

Common “comparator modules” ship with large pull-ups (10–100 kΩ) and an LED to VPU → slow edges and level mismatch.
Fixes: (1) replace pull-up to meet t_r bound; (2) move pull-up to the receiving domain; (3) remove/retime the LED or buffer it.
Check: power-up order, reverse-current paths, leakage vs. divider error, MCU VIH/VIL at temperature.

Comparator module pitfalls: LED to VPU and large pull-up causing slow edges and level mismatch; recommended fixes shown — Typical module traps and remedies: pull-up value/domain and LED buffering.

Debounce & slow inputs →

Validation & Production Notes

Comparator timing depends strongly on ΔVIN, temperature, and supply. Validate with a 3-D sweep, then lock production with statistics (CPK) and sound measurement practice.

Validation flow: ΔVIN × Temperature × VDD sweep to measure TPD, thresholds, hysteresis and jitter; production stats with CPK — Sweep ΔVIN × Temp × VDD → log TPD/thresholds/hysteresis/jitter → qualify with CPK and control charts.

Timing Criterion

Require max(TPD_LH,TPD_HL) ≤ spec and pulse_min ≥ 3×TPD_max.

Hysteresis Criterion

V_hys ≥ 3×V_in,pp (automotive ≥ 4×) and |ΔV_hys|/V_hys ≤ 10% across PVT.

Jitter Budget

Edge uncertainty ≈ σ_T ≈ σ_noise / (dV/dt); target σ_T ≤ τ_min/10.

Measurement Notes

Scope BW ≥ 5×(1/t_r), 10× low-C probe or 50 Ω input; de-embed cable delay; tight local decoupling (0.1 µF + 1 µF).

ΔVIN point (mV)	Temp (°C)	VDD (V)	Pass/Fail criterion	Samples (n)	Lot / Unit / Notes
2	−40	VDD_min	TPD_max & jitter within spec	30	Lot#, Unit#, Fixture
5	25	VDD_typ	Vhys ≥ 3×Vin_pp	30	Lot#, Unit#, Fixture
100	125	VDD_max	σ_T ≤ τ_min/10	30	Lot#, Unit#, Fixture

Sampling & CPK

Per lot/line/shift start with n=30. Compute CPK on TPD, VTH, Vhys; target CPK ≥ 1.33 (≥1.67 preferred).

MSA & Control

Run GR&R for fixtures; track with X-bar/R or I-MR charts; define stop/containment when rules trip.

Common Pitfalls

Tiny ΔVIN inflates TPD; module LEDs slow edges; CMVR edge + temp causes chatter; cross-domain pull-up over-volts MCU; probe loading shifts thresholds.

Download CSV — Validation log Download PDF — Checklist

Patterns & Deep-Dive Previews

Hub cards preview the key comparator patterns. Each card gives a one-paragraph summary, one golden rule, one risk, and one CTA into a spoke page. We keep this section concise to preserve the main page’s vertical intent.

Hysteresis Comparator

Positive feedback creates two thresholds (VTH+ / VTH−) that suppress chatter around the trip point, stabilizing edges on ripple-rich or slow-ramp rails.

Rule: Vhys ≥ 3×Vin,pp (auto ≥4×) Risk: Source impedance reduces effective Vhys

Hysteresis design →

Pull-Up Sizing (OD/PP)

Choose open-drain for level mixing or push-pull for symmetry. Size the pull-up to keep rise time far below the minimum pulse width budget.

Rule: tr ≈ 2.2·R·CL; tr ≤ 0.1·τmin Risk: Missed narrow pulses

Pull-up sizing →

Window Error Budget

Stack reference, divider tolerance, input offset and temperature drift to bound upper/lower thresholds and their pass-band timing skew.

Rule: σ ≈ √(Vref%² + Rdiv%² + Vos%²) Risk: OD OR → asymmetric delays

Window budget →

Debounce & Slow Inputs

For relays/switches/optos, combine RC timing with Schmitt thresholds to reject bounce and slow edges without distorting functional timing.

Rule: τ ≈ 5–10 ms (mechanical) Risk: Over-/under-debounce

Debounce patterns →

Tiny ΔVIN & Narrow Pulses

Overdrive-dependent propagation delay dominates near threshold. Validate minimum detectable width across ΔVIN, temperature and VDD.

Rule: ΔVIN < 5 mV → TPD ↑ Risk: Corner-case misses

Detect narrow pulses →

High-Voltage Inputs & CMVR/Clamp

Protect low-voltage comparators with series-R, TVS/RC, and proper biasing; verify common-mode range near rails and re-measure delay vs. overdrive.

Rule: I_clamp ≤ 1 mA Risk: Clamp skew & delay

HV inputs & CMVR →

Applications (10 domains)

Comparator use cases grouped by topology, key specs, executable rules, risks, and validation notes. Each card previews the essentials and links to an application-specific IC shortlist for procurement.

Power-Good / UV-OV Supervision

Window comparator to assert PG within bounds and flag faults.

Topology: Window + open-drain to PG tree
Key specs: Vhys 1–3%, CMVR near rails, low Iq
Rules: Vhys ≥ 3×Vin,pp; include divider/ref in σ
Risks: Power-up order; OD OR delay asymmetry
Validation: cold-crank/surge/ripple sweeps

IC shortlist →

Zero-Cross Detection

Edge detection for AC sensing and synchronous control.

Topology: Non-inverting + mid-rail bias
Key specs: TPD, input protection to ±HV
Rules: Add Schmitt; filter HF noise
Risks: CMVR edge, high dv/dt injection
Validation: fMAX vs TPD; noise/THD injection

IC shortlist →

Battery Window / Cell Guard

In-range detection for cell voltage protection and alarms.

Topology: Window + OD OR to fault line
Key specs: offset & drift; built-in refs
Rules: σ ≈ √(Vref%² + Rdiv%² + Vos%²)
Risks: High-R divider leakage
Validation: temp sweep + long-term drift

IC shortlist →

Over-Current / Shunt Trip

Trip on shunt voltage or with a front-end current sense amp.

Topology: Inverting threshold
Key specs: ΔVIN sensitivity, TPD
Rules: Ensure ΔVIN ≥ 5–10 mV
Risks: Cold/low-VDD misses
Validation: narrow-pulse train sweep

IC shortlist →

Motor/Encoder Edge Recovery

Square up sensor edges on long/noisy cables for MCU capture.

Topology: Schmitt + OD/PP
Key specs: Vhys, ESD, EMI
Rules: Vhys ≥ 2× noise-pp
Risks: Ringing → add 33–100 Ω
Validation: EMI & cable length sweep

IC shortlist →

Sensor Window Guard (Temp/Pressure)

In-range/out-of-range guard for industrial sensors.

Topology: Window + bias
Key specs: offset, ref accuracy, Iq
Rules: Prefer built-in precision refs
Risks: Drift → false windows
Validation: temp cycling + ADC cross-check

IC shortlist →

Clock Restoration / Squaring

Restore degraded clocks for digital domains.

Topology: High-speed PP comparator
Key specs: tPD, tr/tf symmetry, fMAX
Rules: fMAX ≈ 1/(tr+tf+tPD_LH+tPD_HL)
Risks: Low input slew → jitter
Validation: eye/jitter vs slew sweep

IC shortlist →

ADC SOC / Timing Qualifier

Clean, deterministic edge for start-of-conversion or gating.

Topology: Non-inv + Schmitt; PP
Key specs: deterministic delay, CMVR
Rules: pulse_min ≥ 3×TPD_max
Risks: ΔVIN ≈ 0 → meta-like flutters
Validation: ΔVIN vs SOC timing plot

IC shortlist →

Windowed RPM / Speed Guard

Speed in-range detection with noise-immune thresholds.

Topology: Zero-cross + window + debounce
Key specs: noise immunity, Vhys
Rules: Set τ per sensor; Vhys per ripple
Risks: Mechanical bounce false alarms
Validation: vibration & spectrum tests

IC shortlist →

Mains Presence / Brownout

Detect line presence and brownout with safe isolation margin.

Topology: Rectified sense + divider + Schmitt
Key specs: input protection, CMVR, isolation
Rules: I_clamp ≤ 1 mA; creepage/clearance
Risks: Surge events → TVS + series-R
Validation: surge/ESD/EFT compliance

IC shortlist →

Submit BOM → Get a comparator shortlist

Selection Matrix — 7-Brand Shortlist

① Lock by speed (TPD) & ΔVIN

Match shortest pulse width & overdrive: High-speed ≤10 ns / Mid 10–100 ns / General 0.1–1 µs / Ultra-low-power ≥1 µs.

② Interface & power

OD vs PP, pull-up domain & CL, rise time vs τ_min; RRIO/CMVR near rails; I_q cap for battery.

③ Qual/pack/stock

AEC-Q100, package height, pin semantics, and “in-stock” band (High/Medium/Low) for procurement.

Card fields: TPD bin (ns) · I_q (µA) · CMVR (RRIO/rail headroom) · Output (OD/PP/IOUT) · V_OS grade · AEC-Q100 · Package height · Stock (H/M/L)

Texas Instruments

TLV3501 / TLV3502

Role: High-speed PP

~4.5 ns PP outputs, good tr/tf symmetry; ideal for clock restore/edge recovery at high f_MAX.

TPD: ~4.5 ns (bin ≤10 ns) · I_q: mid
CMVR: RRIO; Output: PP, IOUT symmetric
V_OS: low; AEC-Q100: —; Height: low
Stock: Medium

Why: Deterministic, fast, square edges → narrow-pulse integrity.

TLV3201 / TLV3202

Role: Fast general PP

~40 ns PP, RRIO; balanced speed/power for SOC triggers and timing qualifiers.

TPD: ~40 ns (bin 10–100 ns) · I_q: low-mid
CMVR: RRIO; Output: PP
V_OS: low; AEC-Q100: —; Height: low
Stock: High

Why: “Default fast PP” with wide domain fit and easy routing.

LM2903-Q1 / LM393-Q1

Role: Automotive OD

Dual OD classics for PG/window trees; massive ecosystem, easy wired-AND and second-source.

TPD: ~130–300 ns · I_q: low
CMVR: wide; Output: OD, strong sink
AEC-Q100: Y; Height: varied (SOIC/TSSOP/SOT)
Stock: High

Why: Proven, cheap, everywhere; great for supervision networks.

STMicroelectronics

TS3011

Role: High-speed PP

~8 ns PP with RRIO; robust for clock squaring and fast edge restoration.

TPD: ~8 ns · I_q: mid
CMVR: RRIO; Output: PP
AEC-Q100: —; Height: low
Stock: Medium

Why: Fast & RRIO for compact high-speed domains.

TS3021 / TS3022

Role: High-speed OD

Open-drain high-speed; easy wired-AND and level mixing with pull-up domain control.

TPD: ~20 ns class · I_q: mid
Output: OD; CMVR: wide
AEC-Q100: —; Height: low
Stock: Medium

Why: OD speed with flexible domain interfacing.

TS881

Role: Ultra-low-power

nA-µA class I_q for battery/wearables; perfect for slow sensors & duty-cycled sampling.

TPD: µs bin · I_q: ultra-low
CMVR: wide; Output: OD/PP variants
Stock: Medium

Why: Battery life first; speed is secondary.

onsemi

NCS2200 / NCV2200

Role: Ultra-low-power OD

µA I_q with OD output for watchdog/threshold; automotive NCV variant available.

TPD: µs bin · I_q: ultra-low
Output: OD; AEC-Q100: Y (NCV)
Stock: Medium

Why: Battery projects needing OD & car variants.

LM2903 / LM393 / LM311

Role: Industrial/auto staples

Core OD families with broad packages & second-source; LM311 as classic single with faster edges.

TPD: ~80–300 ns (LM311 faster) · I_q: low
Output: OD; AEC-Q100: options
Stock: High

Why: Easy availability; good for window/PG nets.

Microchip

MCP6561/2/6

Role: Fast PP, RRIO

~20–50 ns PP, RRIO; great for ADC SOC/timing gates with deterministic edges.

TPD: ~20–50 ns · I_q: low
Output: PP; CMVR: RRIO
Stock: High

Why: Solid “fast PP” with good availability.

MCP6541/2

Role: Ultra-low-power

Very low I_q for battery sensors; OD/PP variants; tolerant to slow edges with Schmitt configs.

TPD: µs bin · I_q: ultra-low
Output: OD/PP; CMVR: wide
Stock: Medium

Why: Great for low-power windows/debounce.

Renesas (Intersil)

ISL55110 / ISL55123

Role: Ultra-high-speed

Super-fast comparators for sampling/clock restore where jitter budget is tight.

TPD: sub-ns–few ns · I_q: higher
Output: PP; CMVR: spec-dependent
Stock: Medium

Why: When f_MAX or jitter dominates.

ICL7665

Role: Dual thresholds

Classic dual-window supervisor; simple cell/battery guards without MCU.

TPD: ~100 ns–µs · I_q: low
Output: OD/PP options; AEC: project-dependent
Stock: Medium

Why: Minimalist window protection block.

NXP

LM393 / LM2903 (NXP)

Role: Industrial OD

Workhorse OD comparators with broad packaging and second-source paths.

TPD: ~130–300 ns · I_q: low
Output: OD; CMVR: wide
Stock: High

Why: Easy multi-vendor alignment.

LM311 (NXP)

Role: Faster single OD

Classic single OD with faster response; suits legacy sockets & simple level detection.

TPD: tens of ns · I_q: low-mid
Output: OD; CMVR: wide
Stock: Medium

Why: Drop-in OD with speed headroom.

Melexis

MLX90xxx Sensor ICs (with internal comparator)

Role: Automotive sensing

For projects bound to Melexis brand, use sensor ICs with built-in comparators to realize thresholds/edges without a discrete comparator.

TPD: internal path; I_q: per device
AEC-Q100: Y (sensor lines); Height: per package
Stock: Low–Medium

Note: For general discrete comparators prefer TI/ST/onsemi/Microchip; keep Melexis as domain-specific option.

Submit your BOM (48h) →

BOM & Procurement

Required fields

V_rail / Level domains (cross-domain pull-up?)
V_th / V_hys targets (incl. tolerances)
TPD requirement (shortest pulse, ΔVIN scenario)
Output type / Pull-up domain / C_L estimate
I_q limit (battery) · Temp drift limit
AEC-Q100 (Y/N) · Package height · Second-source plan

Risks & mitigations

Pin/semantic mismatch (OD/PP, VO, EN/REF) — verify before layout
EOL/NRND lifecycle status — avoid fragile SKUs early
Lead time / MOQ for small builds — plan buffer SKUs
Lot variation in TPD vs ΔVIN, V_OS, V_hys — include corner sampling
Second-source alignment of V_th/V_hys/CMVR/IOUT — lab cross-check

Submit your BOM

Send your rails, thresholds, speed & interface constraints. We’ll return a 7-brand aligned shortlist within 48 hours.

/submit-bom →

Example SKUs (why they fit)

TI: TLV3501 — fast PP for edge/clock; LM2903-Q1 — auto OD for PG/window; TLV7011 — low-power RRIO for battery.
ST: TS3011 — ~8 ns PP RRIO; TS3021 — OD high-speed, wired-AND; TS881 — ultra-low-power.
onsemi: NCS2200/NCV2200 — µA I_q OD; LM2903 — industrial/auto staple.
Microchip: MCP6561 — ~50 ns PP for SOC/ADC; MCP6541 — ultra-low-power for slow sensors.
Renesas: ISL55110 — ultra-high-speed, tight jitter; ICL7665 — dual thresholds for simple guards.
NXP: LM393/LM2903 — OD second-source paths; LM311 — faster single OD legacy fit.
Melexis: MLX90xxx sensor ICs with internal comparator — when brand lock requires integrated solution.

FAQs — Voltage Comparator

Hysteresis design Overdrive vs Delay Outputs & Pull-Up CMVR & Clamp Window thresholds Interfacing notes Validation plan Selection matrix BOM & procurement

How large should hysteresis be for 20–50 mV ripple rails?

Use a practical floor of Vhys ≥ 3×Vin,pp for general rails and ≥ 4× for automotive noise. Source resistance reduces effective hysteresis, so buffer or lower the source impedance if trip points still chatter. Validate at worst ripple and temperature corners with the scope’s time-trend to confirm a clean single transition band.