Remote Power Monitors for V/I/T via I²C/PMBus

Remote Power Monitors (Satellite Nodes) place near-load V/I/T sensing with local thresholds and time-stamped alerts, returning telemetry via I²C/PMBus. They suppress long-trace error and ground bounce, improving event fidelity and latency versus centralized monitors. Design goals: trustworthy per-rail evidence under hot-plug and dv/dt, with star/segmented buses, clock-stretch policy, snapshots, and black-box logging.

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1 Answer Box 2 What is it 3 Architecture 4 Mechanisms 5 Key Metrics 6 Design Guidelines 7 Troubleshooting 8 Applications 9 Reference ICs 10 FAQ

Answer Box (one-screen decision)

Takeaway: when trace length > 10–20 cm, return paths are complex, or modules are hot-pluggable, near-load satellite monitors materially improve measurement fidelity and alert latency.

When should you deploy a satellite node?

Trace length > 10–20 cm, cross-board/backplane harnessing.
Noticeable ground bounce or shared-return coupling.
Hot-plug slots or detachable cables causing dv/dt stress.
Centralized sensing shows systematic error during load transients.

Fast decisions

Interface rate × C_bus must meet rise-time & stretch budgets.
CMRR @ dv/dt with input RC and clamps sized.
ADC resolution / averaging latency aligned to event bandwidth.
Temp drift & timestamp plan: 2-point cal + snapshot on alert.

Top-5 pitfalls (with validation moves)

Shunt self-heating → confirm with IR camera & I²R budget.
Wrong Kelvin routing → dual-probe the sense loop symmetry.
Ground reference steps → check differential offset during load steps.
I²C address collisions → power-up scan + isolation policy.
Clock stretch over-limit → host timeout aligned to device max.

Trace length >20 cm: deploy a satellite node.

Hot-plug/shared ground? measure at the load.

Bus capacitance high? split segments or add repeater.

Decision cheatsheet showing when to place near-load satellite power monitors and common pitfalls — answer-card-remote-node-3x2.png · 3:2 · deep-blue theme

Definition & Boundaries (what it is / isn’t)

A remote power monitor (satellite node) is a near-load sensor module that measures voltage, current, and temperature, evaluates local thresholds for alerts (ALERT#/PG/FAULT), and returns telemetry over I²C/SMBus/PMBus (100 k–1 MHz).

Precision

Short Kelvin loops reduce line drop and ground-loop error that plague centralized long leads.

Alert latency

Local comparators + interrupts react faster than poll-only schemes across long buses.

Scalability

Distributed nodes scale by bus segments, address plan, and stretch budget—not by a single long harness.

Typical interfaces: I²C/SMBus/PMBus (100 k–1 MHz) + ALERT#/PG/FAULT. Keep host timeout aligned with device stretch ceiling.

Where centralized sensing often fails (and satellites fix)

Hot-plug dv/dt on long leads causes false trips or missed alerts.
Load-dependent line drop injects a systematic error during transients.
Shared-return inductance produces ground bounce; high-side/low-side readings diverge.
Backplane EMI aliases into the front-end and destabilizes readings.
Long alert paths with poll-only schemes miss short events.
Address/capacitance stacking pushes I²C into timeouts or stretch violations.

Centralized long-lead sensing versus near-load satellite loops; shows return path and error contributors — definition-contrast-3x2.png · 3:2 · contrast of loop length and error sources

Architecture & System Flow

End-to-end path: Sense (V/I/T) → linearize/average → threshold compare → local interrupt & register snapshot → host read via I²C/PMBus.

Near-load analog front-end

Kelvin shunt (or lossless method) → instrumentation/CSA with dv/dt-tolerant input RC and clamps → CMRR@frequency sized for hot-plug edges.

ADC & digital chain

Resolution/INL/DNL; SPS & averaging modes (window/moving/exponential); latency budget and raw vs averaged register mapping.

Thresholds & alerts

Window/slope/integral comparators, latch vs auto-recover, ALERT#/PG/FAULT and read-clear status.

Registers & PMBus/I²C

Address plan; snapshot registers for TS_COUNTER/EVENT_LOG; clock-stretch ceiling aligned with host timeout.

Satellite node architecture with separate data (PMBus/I2C) and alert (ALERT#/PG/FAULT) paths, including shunt, AFE, ADC, averaging and register snapshots — remote-node-architecture-3x2.png · 3:2 · data vs alert path

Bus topology selection

Star: best serviceability (slots/cages). Easy isolation; shorter per-branch C_bus.
Daisy: few nodes & short traces only; maintenance unfriendly; stacking capacitance risks timeouts.
Segmented (repeaters/isolators): use when C_bus or branch length exceeds budget; place boundaries at backplane connectors.

Star, daisy, and segmented I2C/PMBus topologies with Cbus budgeting and pull-up guidance — bus-topologies-3x2.png · 3:2 · topology comparison

Capacitance budget
C_bus ≈ ΣC_trace + ΣC_conn + ΣC_dev

Rise time estimate
t_r ≈ 0.8473 · R_pullup · C_bus

Stretch & host timeout (engineering ranges)
Per-transaction stretch 1–10 ms (≤25 ms max). Host timeout 35–50 ms typical; boot/scan 100–250 ms.

Mode	t_r target	Suggested C_bus	Notes
Standard (100 kHz)	≤ 1000 ns	≤ 400 pF	Longest reach; use segmented topology if branches proliferate.
Fast (400 kHz)	≤ 300 ns	≤ 200 pF	Backplane friendly with short stubs; avoid heavy device capacitance.
FM+ (1 MHz)	≤ 120 ns	≤ 100–150 pF	Prefer per-slot branches; repeater boundaries at connectors.
HS (3.4 MHz)	tight	≤ 50–80 pF	Short segments only; use dedicated HS transceivers.

Mechanisms & Design Physics

1 High-side / Low-side measurement & CMRR

High-side avoids load-return ground bounce but demands stronger CMRR@dv/dt and robust input protection. Low-side is simple yet inserts loop drop and can disturb system behavior.

Size input RC and clamps so the S/H network can settle across hot-plug edges.
Place ESD/EMI hooks at the connector and keep Kelvin pair symmetric to the shunt pads.

High-side and low-side current sensing with dv/dt injection paths and CMRR focus points — high-vs-low-side-3x2.png · 3:2 · dv/dt and CMRR focus

Dynamic error (approx.): V_err ≈ (dv/dt) · Z_coupling / A_CMRR(f). Verify with load-step and differential probe.

2 Shunt selection

Balance range, resolution, and thermal drift. Specify Kelvin pads and keep sense loop independent from the power loop.

Shunt self-heating isotherms and curves showing power versus temperature rise — shunt-thermals-3x2.png · 3:2 · thermal behavior and TCR

P_shunt = I² · R

ΔV_gain ≈ I · ΔR, where ΔR ≈ R · TCR · ΔT

3 ADC & digital chain

Averaging increases SNR roughly with √N but adds latency. Use a dual-track strategy: raw channel for events; averaged channel for reports.

Charts of SNR improvement versus averaging and latency versus sampling rate — adc-averaging-latency-3x2.png · 3:2 · SNR vs averaging, latency vs SPS

SNR_avg ≈ SNR_raw + 10·log10(N). Moving average improves noise but smears step response—keep an event-rate bypass.

4 Temperature path

Temperature supports gain compensation and protection. Prefer two-point calibration; validate thermal coupling with on-board trials near inductors and hot FETs.

Thermal coupling paths from hot sources to temperature sensors on the PCB — temp-sensing-placement-3x2.png · 3:2 · sensor placement and coupling

Error budget = Sensor accuracy + Thermal gradient + ADC quantization. Use at least two probes around hotspots to validate gradient.

5 Alarms & debounce

Window + integral/slope comparators resist short-lived spikes better than single thresholds. Latch for safe shutdown; auto-recover for transient excursions.

Waveforms comparing single-threshold false trips versus window plus integral filtering with latch/clear behavior — alarm-windows-3x2.png · 3:2 · window/integral alarms

Acceptance: state a target false-alarm rate, a minimum inhibit time, and hysteresis width to avoid reset storms.

6 Bus integrity

Make C_bus the first-class constraint: compute it, back-solve R_pullup, then decide to segment or elevate to FM+. Check device I_OL so pull-up current is within limits.

I2C bus capacity budget bars for traces, connectors and devices, with pull-up guidance per mode — i2c-capacity-budget-3x2.png · 3:2 · capacity budget and pull-ups

t_r ≈ 0.8473 · R_pullup · C_bus. When C_bus > 200 pF @ 400 kHz or > 100–150 pF @ 1 MHz, segment the bus or add a repeater.

7 Timestamping & alignment

Align all nodes to a common host time base. On alerts, capture a snapshot of raw and averaged registers so reconstruction is deterministic even with stretch and poll delays.

Timeline from sampling to register snapshot to alert interrupt and host read with a unified time base — timestamping-alignment-3x2.png · 3:2 · snapshot and host alignment

Cross-node target: ±1–2 ms alignment under load. Use read-clear or indexed logs to avoid duplicate retrieval.

8 Safety & fault containment

No single segment/node failure should stall the fleet. Add fail-safe pull-ups, address-conflict detection at boot, and line-break/short detection. Isolate failing branches so the host can keep polling survivors.

Local fault tree showing cable open or short, address mismatch and isolation so remaining nodes keep responding — fault-containment-3x2.png · 3:2 · isolate and keep polling

Acceptance: after isolating a bad branch, the host still receives ACKs and telemetry from remaining segments; event logs remain readable.

Key Specification Matrix (fields & acceptance)

Purpose: unify evaluation fields and measurement methods so purchasing, design, and validation share one yardstick. Each field includes a single-sentence method (acceptance) to avoid mismatched criteria.

C_bus ≈ ΣC_trace + ΣC_conn + ΣC_dev

t_r ≈ 0.8473 · R_pullup · C_bus

Clock stretch per transaction 1–10 ms (≤25 ms max). Host timeout 35–50 ms typical; boot/scan 100–250 ms.

Group	Field	Spec & Unit	Method (Acceptance)	Notes
Measurement
Measurement	V_range	e.g., 0…16 V	@25°C, nominal VDD; error holds across full temp	State absolute max and headroom
Measurement	I_range	e.g., ±100 A	Bidirectional if stated; shunt not in thermal limit	Include pulse SOA
Measurement	Resolution	e.g., 15.3 µV / 0.8 mA	LSB @ selected SPS/avg; exclude digital filter gain	Report raw vs averaged LSB
Measurement	INL	e.g., ±0.05 % FS	@25°C, no-load, 1×FS; end-point method	Show linear-fit error if used
Measurement	Gain_error	e.g., ±0.1 %	@25°C, no-load, 1×FS; after zero/gain cal	State cal procedure
Measurement	Temp_drift	e.g., 40 ppm/°C	25→85/105°C slope; include shunt TCR if on-board	Quote typ & max if available
Front-end
Front-end	CMRR@f	e.g., 100 dB@100 kHz; 80 dB@1 MHz	Measure with dv/dt steps; ensure no overflow	Specify test fixture & probe
Front-end	Input_filter	RC time constant	RC matches ADC S/H; settling ≥ 2×τ before hold	Document RC placement
Front-end	ESD/EMI	IEC61000-4-2 or app-level	Connector clamps verified	Clamp type & levels
Shunt
Shunt	R	e.g., 0.5–10 mΩ	Measured @25°C; tolerance ±x%	Four-terminal Kelvin
Shunt	P_max	e.g., 3 W cont.	ΔT ≤ ΔT_allow; check pulsed SOA	Thermal photo @ worst case
Shunt	TCR	e.g., 50 ppm/°C	25→100°C slope; include in gain drift budget	Material system
Shunt	Pkg	e.g., 2512, 3920	Land pattern supports Kelvin	θJA note if relevant
Shunt	Kelvin_note	—	Sense pads symmetric to inner shunt	Avoid crossing power path
ADC
ADC	Bits	e.g., 16–20 ENOB	Effective bits; exclude averaging inflation	State OSR if sigma-delta
ADC	SPS	e.g., 1 ksps raw	Max SPS in mode; stretch within budget	List valid SPS steps
ADC	Latency	e.g., 2–10 ms	Pipeline + averaging; edge-to-valid measured	Report per mode
ADC	Averaging_modes	window/moving/exponential	Raw bypass for events	Default coefficients
Alarms
Alarms	UV/OV/OC/OT	thresholds & accuracy	@25°C; drift over temp noted	Absolute vs ratioed thresholds
Alarms	Window/Slope/Integral	integration window	Step rejection demonstrated	Min inhibit time
Alarms	Response	e.g., < 2 ms	Alert-to-interrupt latency @ Y SPS	Measurement method
Alarms	Latch	latch/auto-recover	Clear method (read-clear)	Default on power-up
Interface
Interface	I2C/SMBus/PMBus	logic levels	Pull-ups per mode; I_OL not exceeded	Voltage domain stated
Interface	Rate	Std/Fast/FM+/HS	Per-branch C_bus checked	Mode per segment
Interface	Addr_count	e.g., up to 16	Unique per slot; boot collision scan	EEPROM/strap plan
Interface	Clock_stretch(ms)	e.g., ≤ 10 ms	Per transaction; host timeout ≥ N+Δ	Worst-case conversion stated
Timing
Timing	Timestamping	±1–2 ms cross-node	Common host time base	Drift if free-running
Timing	Snapshot	raw + averaged	Alert-triggered; read-clear	Indexed if multi-event
Timing	Sync_method	poll + interrupt	Jitter budget stated	Bus analyzer traces
Power
Power	VDD/VIO	operating window	UVLO/OVP thresholds noted	Separate I/O domain
Power	ICC(run/standby)	e.g., 2.5 mA / 20 µA	@25°C typical	Standby wake sources
Power	T_range	e.g., −40…+125°C	Operating; derating if any	Storage separate
Package
Package	Footprint(mm²)	body + keep-out	Height if relevant	Connector clearance
Package	θJA	JEDEC 4-layer board	Airflow assumptions	Measurement setup
Compliance
Compliance	EMC	front-end RC/clamp placement	Cable shield scheme	Ground zoning note
Compliance	Safety	isolation type (if any)	creepage/clearance	Ratings and standards

spec-matrix-remote-3x2.png · 3:2 · field mapping schematic

Design Rules (10 items with verification)

Ten actionable rules. Each card includes Why, How to verify, Acceptance, and a common Pitfall. Instruments: IR camera, differential probes, oscilloscope, bus/logic analyzer.

1) Shunt thermal drift: size R from I_max & ΔT_allow

Why: I²R self-heating moves gain via TCR.
Verify: steady-state & pulsed IR imaging; pre/post linear fit.
Acceptance: ΔT ≤ target; equivalent gain drift ≤ budget.
Pitfall: ignoring pulsed SOA and thermal time constants.

2) Kelvin routing: symmetric sense close to inner pads

Why: prevents power loop drop from polluting measurement.
Verify: twin-probe check of sense loop symmetry.
Acceptance: step-load offset ≤ X mV.
Pitfall: sense taken from outer pads or across high-current paths.

3) Input RC matches ADC S/H; pulse hold ≥ 2×τ

Why: inadequate S/H charging distorts edges.
Verify: step injection; observe phase & recovery.
Acceptance: hold ≥ 2×τ; no false trips from over/undershoot.
Pitfall: oversizing RC and slowing the front-end.

4) CMRR & dv/dt immunity with clamps and zoning

Why: hot-plug/ground-bounce injects common-mode steps.
Verify: fast load steps; watch input over/undershoot and saturation.
Acceptance: CMRR @100 kHz/1 MHz met; no overflow.
Pitfall: missing clamps near the connector.

5) Bus capacity first: back-solve R_pullup; segment first

Why: excessive C_bus breaks rise-time/timeout limits.
Verify: compute C_bus; scope t_r.
Acceptance: t_r ≈ 0.8473·R_pullup·C_bus fits mode; segment before FM+/HS.
Pitfall: shrinking R_pullup until I_OL is exceeded.

6) Address plan with strap/EEPROM; hot-plug collision test

Why: duplicate addresses stall the bus.
Verify: boot scan & forced collision isolation.
Acceptance: conflict detected and isolated; other nodes still ACK.
Pitfall: relying on fixed addresses without collision tests.

7) Alarm strategy: window + integral; thresholds from data

Why: reduces false positives versus single thresholds.
Verify: record distributions → set window & integral → re-measure false-alarm rate.
Acceptance: false-alarm rate ≤ target; no reset storms (min inhibit/hysteresis).
Pitfall: hard single threshold causing chatter.

8) Temperature calibration: two-point first; online bias later

Why: compensates gain and protection drift.
Verify: two-point fit; add online bias tracking.
Acceptance: residual ≤ target; coefficients versioned.
Pitfall: single-point only or ignoring thermal coupling.

9) Dual-track data: raw for events, averaged for reports

Why: averaging improves SNR but hides spikes.
Verify: event channel bypasses averaging; report channel averages.
Acceptance: event capture rate met; report stability achieved.
Pitfall: global averaging causing missed events.

10) Black-box logging: alert → snapshot → read, unified time base

Why: reproducible reconstruction under power loss and jitter.
Verify: interrupt-triggered snapshot; host-time alignment.
Acceptance: ±1–2 ms cross-node; logs remain readable.
Pitfall: missing read-clear/index, causing duplicates.

Ten design rules for satellite power monitors rendered as cards — ten-design-rules-3x2.png · 3:2 · ten-rule overview

Troubleshooting Matrix (Symptom → Observe → Cause → First Action → Tools)

Use the leftmost Symptom to jump to Observable fields and apply the First Action. Verify with the suggested Tools, then lock in Prevent so the issue does not recur.

Key logs/registers: TS_COUNTER, EVENT_LOG, ALERT_SRC, SNAP_VALID, ERR_NACK, STRETCH_MS.

Symptom	Observable	Likely Cause	First Action	Tools	Confirm	Prevent
Reading drifts with temperature	T_shunt, gain trend, IR photo	Shunt TCR / self-heating	Lower R or redistribute power + 2-point compensation	IR camera, multi-channel logger	Steady/pulse IR before/after; fit residual drift	Budget ΔT_allow; include TCR in gain budget
Alarm chatter	Pulse width, edge density, false-rate	Debounce too weak	Enable integral/hysteresis/min hold	Logic analyzer	False-rate ≤ target under stress	Thresholds from data distribution
Transient events missed	Event count holes, missing snapshots	Averaging too large / link latency	Bypass avg; open fast window; raise event bandwidth	High-speed oscilloscope	Pulse-inject capture rate ≥ target	Dual-track: raw for events, avg for reports
Random NACK on bus	Stretch timeouts, rise time t_r, ACK loss	Weak pull-up / excessive C_bus	Segment or buffer; adjust pull-ups	Bus analyzer	t_r ≈ 0.8473·R_pullup·C_bus meets mode	Capacitance budget; segment at connectors
Cross-board bias	Diff offset during load steps	Ground bounce / return loop	Kelvin fix; star-ground routing	Differential probe	Offset ≤ threshold under steps	Near-load nodes; ground zoning
Address conflict after hot-plug	Duplicate scan entries, conflict log	Fixed address overlap	Dynamic assign / DIP; isolate conflict	Host scan script, bus analyzer	Others ACK after isolation	Strap/EEPROM plan + boot self-check
ADC saturation / clipping	Raw code near rails, stuck alerts	Range too small / AFE overdrive	Increase range; add clamps/limiters	Scope + raw register dump	No clipping under worst-case	Range review vs load profile
Temperature hysteresis	Up/down curves do not overlap	Poor coupling / airflow	Relocate sensor; TIM; 2-point cal	Heat gun + IR	Hysteresis < target	Place near inductor/FET hotspots
Alarm storm (resets loop)	Reset count, alert queue bursts	No hysteresis / min hold	Add hysteresis + inhibit time	Logic analyzer + host logs	Storm eliminated on stress test	Integral windows; guard timers
Isolator/repeater sticky (SDA/SCL low)	SDA stuck, HS not achieved	I_OL exceeded / level mismatch	Re-size pull-ups; match level domains	Bus analyzer	Consistent levels across domains	Device selection with margin
Timestamp drift across nodes	TS differences, event reorder	No sync / missing snapshot	Unify host time; ALERT→SNAP→READ	Host sync script	±1–2 ms cross-node	Periodic sync; read-clear logs
False OC due to noise	Narrow spikes trigger alarms	Front-end RC mismatch / missing clamps	Match RC to S/H; add connector clamp	Fast-edge scope	No trips on injected pulses	ESD/EMI hooks placed at connector
ALERT# stuck active	ALERT pin low; status latched	Missing read-clear / threshold too tight	Implement read-clear; review thresholds	Logic analyzer + host script	ALERT clears and re-arms	ISR enforces clear + logging
Host timeout false positives	Timeouts only during boot scans	Excess stretch from deep averaging	Raise boot timeout; shorten averaging	Bus analyzer	No timeouts with new params	Per-mode timeout table

Decision tree from symptom to observation and first action for satellite power monitors — troubleshooting-tree-3x2.png · 3:2 · symptom→observe→action

Applications & Reference Solution Skeletons

Scenario A — Server/Storage Backplane (NVMe / U.2 / U.3)

Topology: one node per slot; Star or Segmented with boundaries at backplane connectors; ALERT# aggregated to CPLD.
Node: shunt 1–5 mΩ; event channel ≥ 1 ksps raw; window+integral alarms; black-box logging (Alert→Snapshot→Read).
Validation: hot-plug + load steps; bus analyzer for t_r and stretch; target false-rate achieved.

Backplane deployment: per-slot satellite nodes, star/segmented bus, ALERT lines merged into CPLD — deployment-backplane-3x2.png · 3:2 · slots, pull-ups, segmentation

Scenario B — Telecom / Industrial Chassis

Topology: Segmented with repeaters or isolation bridges; boundaries at board-to-backplane or cable connectors.
Node: shunt 2–10 mΩ; temperature sensors placed near inductors/FETs; raw events bypass averaging.
Validation: dv/dt injection on harness; ESD clamp test; C_bus budget vs measured t_r.

Chassis deployment: segmented I2C/PMBus with isolators at connectors and nodes per board — deployment-chassis-3x2.png · 3:2 · segments, isolators, shields

Scenario C — Automotive Domain Controller

Topology: near-load satellite nodes + segmented bus; isolation on critical branches; surge-aware design.
Node: shunt 5–20 mΩ; window+integral alarms; mandatory black-box logging; unified time base (±1–2 ms).
Validation: load pulses, cold-crank, surge tests; false-rate and capture-rate pass criteria.

Automotive deployment: near-load nodes, isolated bus segments, and black-box logger for Alert → Snapshot → Read — deployment-automotive-3x2.png · 3:2 · isolation & logging

Scenario D — Edge AI / Accelerator Board

Topology: per power domain node; Star or short segmented; telemetry linked to DVFS limits.
Node: shunt 0.5–2 mΩ; raw channel high bandwidth; report channel averaged; slope/integral windows.
Validation: composed pulsed loads; power-limit response time evaluated.

Accelerator deployment: nodes per power domain with DVFS table linkage — deployment-accelerator-3x2.png · 3:2 · domain nodes & DVFS

Scenario	Shunt (mΩ)	Connectors	Pull-ups (kΩ)	Repeaters / Isolators	Cables / Shield	Logging & TS
Server/Backplane	1–5	High-cycle, shielded	1–3 (per segment)	FM+/HS repeaters at slots	Short stubs, shield to chassis	Alert→Snap→Read; ±1–2 ms
Telecom/Chassis	2–10	Backplane/cable connectors	1–4 (split by branches)	Isolation bridges at connectors	Shielded cables, drain wire	Event log indexed
Automotive	5–20	Automotive-grade	2–4 (temp & surge aware)	Isolated segments at harness	Braided shield, surge arresters	Black-box mandatory
Edge AI/Accelerator	0.5–2	High-current board-to-board	1–3 (short segments)	HS repeaters if needed	Short, low-inductance harness	DVFS-linked telemetry

Reference ICs & Equivalents

Scope: neutral, vendor-agnostic shortlists to seed evaluation for remote (satellite) power monitors. No ratings or reviews. Each table is a category with comparable parts and the selection dimensions you’ll actually decide on: CMRR@frequency, SPS×Latency, Addr planning, Clock-stretch, T_range.

Methodology footnote: CMRR @ 100 kHz / 1 MHz step (dv/dt); Latency = pipeline + averaging; INL/Gain_error @ 25 °C, 1×FS, no-load; Stretch ≤ N ms/txn, host timeout ≥ N+Δ. Values are vendor-datasheet dependent—treat below cells as capability notes, not guaranteed specs.

A. I²C/PMBus Voltage/Current/Power Monitors (hi/low-side, 16–20-bit, alarms/averaging/snapshot)

MPN	Function	Sense / CMRR@f	ADC Bits / SPS × Latency	Addr options	Clock-stretch (ms)	T_range	Pkg	Notes
TI INA226	V/I/P monitor (I²C)	High-side CSA; PWM-tolerant	16-bit ΣΔ; up to ~1 ksps; mode-dep latency	Pin-strap	Supports; budget per txn	−40…+125 °C	TSSOP/SO	Popular baseline
TI INA230/INA231	V/I/P monitor	High-side	16-bit class; avg/alert	Pin-strap	Yes	−40…+125 °C	QFN/TSSOP	Multi-vendor adoption
TI INA238	V/I/P monitor	High-side; fast step	16-bit+; low latency options	Pin-strap	Yes	−40…+125 °C	QFN	Event capture focus
TI INA228	High-accuracy V/I/P	High-side; high CMRR	Up to 20-bit eff.; avg/snap	Pin-strap	Yes	−40…+125 °C	QFN	Advanced telemetry
ADI LTC2991	Multi-channel monitor	Diff sense; muxed	16-bit class; multi-SPS	Pin-strap	TBD by mode	−40…+125 °C	QFN	V/I/T mix
ADI LTC2992	Dual channel power	High-side	16-bit ΣΔ; energy accum.	Pin-strap	Yes	−40…+125 °C	QFN	On-chip energy
ADI LTC2946	Wide-range power	High/low-side options	16-bit class; fast read	Pin-strap	Yes	−40…+85/125 °C	QFN/TSSOP	Accumulators
Microchip PAC1931/2/3/4	1–4ch power monitor	High-side	16-bit class; accum./avg	Pin-strap	Yes	−40…+85/125 °C	QFN/TSSOP	Multi-rail
Renesas ISL28022/23	Power monitor (SMBus)	High-side; robust	16-bit class	Pin-strap	SMBus stretch	−40…+125 °C	QFN	Server backplanes
Maxim MAX34406/07	Multi-rail monitor	High-side	16-bit class; energy	Pin-strap	Yes	−40…+105 °C	QFN	Data center focus

B. Precision Current-Sense Amplifiers (wide common-mode / transient-robust)

MPN	Function	Sense / CMRR@f	ADC Bits / SPS × Latency	Addr options	Clock-stretch (ms)	T_range	Pkg	Notes
TI INA240	CSA (PWM rejection)	High-side; high CMRR@PWM	—	—	—	−40…+125 °C	TSSOP/SOIC	Motor/inductor loads
TI INA281/INA282	CSA (high-speed)	Wide CM; fast edges	—	—	—	−40…+125 °C	SOT-23	Fast transient
TI INA199 / INA190	Low-power CSA	High-side; compact	—	—	—	−40…+125 °C	SOT-23	Small rail monitors
TI INA290	High-precision CSA	High CMRR; low drift	—	—	—	−40…+125 °C	SOT-23	Precision loads
ADI AD8418 / AD8417	Bidirectional CSA	Automotive-grade CMRR	—	—	—	−40…+150 °C*	SOIC	A/B domain
ADI AD8210 / AD8207	High-side CSA	Wide CM; robust	—	—	—	−40…+125/150 °C*	SOIC	Legacy proven
Maxim MAX4080 / MAX4081	Bidirectional CSA	High-side; fast	—	—	—	−40…+125 °C	SOIC/TSSOP	General purpose
Microchip MCP6C02 / MCP6C04	High-side CSA	Fast step; low offset	—	—	—	−40…+125 °C	SOT-23	Compact front-end

C. Temperature Sensors (local + remote thermal-diode interfaces)

MPN	Function	Sense / CMRR@f	ADC Bits / SPS × Latency	Addr options	Clock-stretch (ms)	T_range	Pkg	Notes
TI TMP451 / TMP461	Local + remote diode	Remote diode filtering	12–16-bit class	Pin-strap	Yes/SMBus	−40…+125 °C	MSOP/QFN	Heatsink sensing
TI TMP1075 / TMP75	Local digital temp	—	12-bit class	Pin-strap (multi addr)	—	−40…+125 °C	SOT-23/SOIC	Drop-in local sensor
ADI ADT7461A	Remote diode + local	CPU/GPU diode	12-bit class	Pin-strap	SMBus	−40…+125 °C	MSOP	Legacy server use
ADI ADT7420 / ADT7410	Local high-accuracy	—	16-bit class	Pin-strap	—	−40…+125 °C	MSOP/TSSOP	Cal-friendly
Maxim MAX6680 / MAX6690	Remote diode + local	Remote diode filter	12-bit class	Pin-strap	SMBus	−40…+125 °C	TSSOP	Fan-control ecosystems
Maxim MAX31875	Local digital temp	—	12-bit class	Pin-strap	—	−40…+125 °C	WLP/SOT	Tiny footprint
LM75A (multi-sourced)	Local digital temp	—	9–12-bit variants	3-bit addr strap	—	−40…+125 °C	SOIC/TSSOP	Commodity choice

D. I²C Repeaters / Isolation Bridges (long line / segmentation)

MPN	Function	Sense / CMRR@f	ADC Bits / SPS × Latency	Addr options	Clock-stretch (ms)	T_range	Pkg	Notes
NXP P82B715	Bus extender	—	—	—	Supports	−40…+85/125*	SO	Long runs
NXP P82B96	Buffer/level	—	—	—	Yes	−40…+85/125*	SO/TSSOP	Domain bridging
NXP PCA9615	Differential I²C	—	—	—	Yes	−40…+85/105*	TSSOP	Cable runs
NXP PCA9517 / PCA9515A	Bidirectional buffer	—	—	—	Yes	−40…+85/105*	TSSOP	Stub isolation
TI TCA4311A	Hot-swap buffer	—	—	—	Yes	−40…+105 °C	TSSOP	Slot cards
TI TCA9803	Level-shift buffer	—	—	—	Yes	−40…+125 °C	SOT	Multi-VIO
TI ISO1540 / ISO1541	I²C isolator	—	—	—	Transparent	−40…+125 °C	SOIC	Galvanic isolation
ADI ADuM1250 / 1251	I²C isolator	—	—	—	Transparent	−40…+125 °C	SOIC	Isolated domains
ADI LTC4310	Differential I²C pair	—	—	—	Yes	−40…+125 °C	SSOP	Long cable over twisted pair
ADI LTC4311	Rise-time accelerator	—	—	—	N/A	−40…+125 °C	SOT-23	Large C_bus help
ADI LTC4317	Bus recovery / addr repair	—	—	Addr masks	Yes	−40…+125 °C	SSOP	Hot-plug friendly

Need a neutral cross-vendor shortlist and eval samples?

Contact Ersa Electronics for a brand-agnostic comparison list and evaluation samples — including bundled BOM for shunts, connectors, repeaters/isolators. NDA support available for register maps and bring-up scripts (address scan, clock-stretch profiling, timestamp sync).

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FAQ — Remote Power Monitors (12 answers)

Practical, vendor-agnostic answers. Each entry gives a “why → how → verify” loop and aligns with earlier sections on topology, bus timing, alarms, and logging.

How do we plan multi-node addresses to avoid hot-plug conflicts?

Reserve a static DIP/strap range per slot, then serialize each board in EEPROM with a unique suffix read at boot. The host performs a startup scan, quarantines duplicates, and assigns a temporary fallback if needed. Log conflicts to aid service. Validate with scripted hot-plug, ensuring unaffected nodes ACK and the bus remains responsive.

When bus capacitance is high, should we segment or add a repeater?

Always segment first at connectors or cable boundaries, keeping each branch within its rise-time budget. Estimate with C_bus ≈ ΣC_trace + ΣC_conn + ΣC_dev and t_r ≈ 0.8473·R_pullup·C_bus. Only add repeaters/isolators if segmentation still fails targets. Re-measure t_r and stretch margins using a bus analyzer after each change.

Should Kelvin sense points sit closer to the load or the connector?

Prefer the load end. Measuring across the connector includes variable contact and harness drops that distort regulation and telemetry. Keep sense traces symmetric, short, and away from high current paths. Verify with a differential probe during step loads: the load-end Kelvin pair yields lower error and smaller dynamic offsets than connector-referenced taps.

How do we maintain CMRR under high dv/dt conditions?

Match the input RC to the ADC sample-and-hold so the front-end settles before conversion. Place clamps at the connector, use shielded routing, and keep analog/digital grounds zoned with a single-point tie. Validate with fast load steps: no overflow, minimal overshoot, and stable recovery indicate sufficient CMRR and dv/dt immunity.

When are alarm windows with integration better than single thresholds?

In noisy or bursty environments, window plus integral filtering reduces false positives by requiring duration, not just amplitude. Set minimum hold time and hysteresis based on measured distributions. Acceptance is a target false-alarm rate under stress tests. Use logic analyzer captures to confirm that chatter disappears while genuine faults still assert.

How do we capture short bursts while averaging is enabled?

Use dual-track data: the event channel bypasses averaging (raw, fast window, minimal latency), while the reporting channel applies averaging for stability. Validate with pulse injection and confirm event capture rate meets targets. Keep alerts latched until snapshot is read to avoid missing closely spaced bursts under host polling jitter.

How many calibration points are needed for temperature channels?

Two-point calibration is preferred to capture slope and offset. Add an online bias correction if packaging or airflow shifts thermal coupling over time. Record coefficient versions for traceability. Validate with controlled ramps and verify residual error across the operating range, including locations near inductors and power devices.

How do we record the last event on power loss and keep time aligned?

Use Alert-triggered snapshots, then read-clear in the ISR or high-priority thread. Synchronize all nodes to a host time base and target ±1–2 ms cross-node alignment. On brownout, capture the final snapshot and sequence numbers. Post-mortem reconstruction relies on consistent timestamps and monotonic event indices across nodes.

What EMI issues affect I²C, and how can we mitigate them?

Long cables, stubs, and poor shielding inflate C_bus and invite interference. Keep stubs short, segment at connectors, size pull-ups per rise-time limits, and use shielded or twisted-pair runs. Where necessary, adopt differential or isolated bridges. Verify with bus analyzer eye captures and ESD surge tests at cable entry points.

How should clock stretching interact with host polling and timeouts?

Define a per-transaction stretch ceiling and set host timeouts to N+Δ with margin for worst-case conversions and averaging. Use lighter modes during boot scans to avoid needless timeouts. Log stretch duration per device, and alert if it exceeds policy, indicating mis-sized pull-ups, excessive C_bus, or heavy filtering.

How can we minimize standby power without losing observability?

Throttle sampling and park noncritical channels; enable event-driven wake and shorter conversions on entry. Keep black-box logging active with minimal metadata so incidents remain traceable. Validate wake latency and confirm alerts still meet response targets. Publish a mode table showing current draw, sampling rate, and resume times.

How do we preserve register compatibility when swapping parts?

Introduce a thin hardware-abstraction layer and capability bitmap negotiated at startup. Keep a self-test that probes key registers and masks unsupported features. Provide fallbacks for alarms, averaging, and timestamp modes. Maintain versioned mapping tables so firmware can translate differences without touching higher-level telemetry pipelines.