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Central Idea

This page distills practical methods for accurate, fast, and robust current measurement using current sense amplifiers and shunt monitors. It links device choices and design rules (R_shunt, PGA, RC filters, thresholds) to real workloads—VRM rails, USB-PD/battery ports, motors/heaters, and multi-rail servers—so you can set repeatable protections, clean telemetry, and traceable calibration with minimal false trips. Layout guidance (Kelvin routing), error budgeting, validation matrices, and PMBus/alert orchestration turn the recipes into a production-ready flow, from lab bring-up to fleet analytics.

Current Sense Amplifiers & Shunt Monitors

One-line scope: High-accuracy shunt monitors with wide common-mode range, power calculation, and fast alarms for dynamic loads.

This page focuses on shunt-resistor–based current sensing chains: high-accuracy measurement under wide common-mode rails (e.g., 12 V/48 V/USB-PD), with power calculation and fast alarms to support protection linkage and PDN/AVP optimization.

Typical applications: battery charge/discharge monitoring, server/accelerator VR rails, motor/heater pulsed loads, automotive 12 V/48 V rails, USB-PD port limiting/metering.
Scope & boundaries: isolation amplifiers/Σ-Δ modulators/digital isolation and magnetic/Hall solutions are covered on sibling pages. Here we only cover shunt + amplifier/monitor + alarms + telemetry (I²C/PMBus).

Typical applications: battery charge/discharge, VR rails, motor loads, 12V/48V automotive, and USB-PD port limiting. — Typical scenarios — Battery, VR rails, motor/pulsed loads, 12 V/48 V automotive, USB-PD ports

Principle

Shunt method: the core relation is V_shunt = I × R_shunt. Sampling can be single-ended or differential; uni- or bi-directional (via zero-point bias or register offset).

Common-mode voltage (VCM) & input swing: a wide VCM range enables high-side sensing on 0–60 V/80 V rails; ensure the amplifier input range covers VCM ± signal.

Low-side vs High-side: low-side is simpler but may disturb the ground return and inject ground noise; high-side preserves ground continuity and is preferred for port limiting/automotive rails.

Power calculation: P = V_BUS × I. Distinguish instantaneous/average/window-integrated power. Select conversion time/bandwidth to capture load steps so peaks are not over-averaged.

Shunt-based sensing: differential voltage across Rshunt with single-ended/differential and uni/bidirectional modes. — Shunt principle — V_shunt = I × R_shunt; single-ended/differential; uni/bi-directional

High-side versus low-side sensing trade-offs in ground integrity, noise, and protection. — High-side vs Low-side — trade-offs in ground continuity, noise, and protection paths

Power calculation flow: I from shunt, VBUS sampling, instantaneous and averaged power windows. — Power calculation — combine I (from shunt) with VBUS; record both instantaneous and averaged power

Architecture

The shunt-based current sensing chain is organized as: Input front-end (filter/ESD) → CSA/SM → ADC/compute → Alerts/PG/PMBus → MCU/PMIC. It targets wide-VCM rails and fast-changing loads where both accuracy and latency matter.

Input front-end: RC filter, ESD/TVS, Kelvin pick-off from the shunt pads; ensure symmetry and short loops.
CSA/SM: gain/PGA selection, offset/bias for bi-directional sensing, input range vs VCM and clamps.
ADC/compute: conversion time and averaging, current/power registers, scaling and calibration constants.
Alerts/PG/PMBus: trip thresholds, hysteresis and delay, mask/enable and status; latency budgeting.
MCU/PMIC: FW hooks, interrupt servicing, black-box logging for field correlation.

Functional blocks for shunt-based current sensing: filter/ESD, CSA, ADC/compute, alerts/PG/PMBus, and MCU/PMIC. — Functional blocks — filter/ESD → CSA → ADC/compute → alerts/PG/PMBus → MCU/PMIC

Interfaces

I2C/SMBus/PMBus: set conversion time/averaging, read current/power, program thresholds; guard bus latency vs alarm response.
ALERT/PG line: hardwire fast trips to protection devices (e.g., eFuse/Hot-Swap); debounce or queue in firmware if needed.
GPIO interrupt: use dedicated IRQ for time-stamped events; keep ISR short and defer parsing.

Optional modules

Power isolation: when the sense domain floats or safety rules apply; budget error from isolator offset/gain.
Divider/shunt-range switch: extend measurable range; re-calibrate after switching to maintain accuracy.
Calibration switch matrix: line-calibration for production; log post-cal constants for traceability.

Design Rules

Rshunt selection

Rule: size Rshunt from allowable drop and power, then confirm resolution and ADC code spread.

Why: drop raises dissipation and reduces efficiency; too small a value hurts resolution and noise margins.

Pitfall: self-heating and TCR drift skew calibration over temperature.

Rshunt selection trade-offs: drop, power, resolution, and thermal drift (TCR). — Rshunt selection — drop, power, resolution, TCR/self-heating

Gain/PGA configuration

Rule: choose the lowest gain that still meets LSB targets; verify the −3 dB point against step-load edge rates.

Why: excessive gain narrows bandwidth and amplifies offset; insufficient gain wastes ADC codes.

Pitfall: too-narrow bandwidth hides inrush/OC peaks.

Common-mode range

Rule: ensure VCM headroom ≥ max rail + transients; check input swing and protection clamps.

Why: wide-VCM parts (e.g., 0–80 V or −0.3 to +80 V) avoid saturation on automotive/PD ports.

Pitfall: front-end RC or TVS clamps can distort at high VCM.

Bi-directional measurement

Rule: center codes at mid-scale via zero-bias or register offset; log direction bits in firmware.

Why: symmetrical headroom for charge/discharge or source/sink currents.

Pitfall: bias drift with temperature degrades small-current accuracy.

Front-end filtering

Rule: place a differential RC close to sense pins; size a slower common-mode RC (5–10×) to tame EMI.

Why: differential RC preserves signal shape while CM RC dampens rail noise.

Pitfall: excessive phase lag near thresholds causes false trips.

Front-end filtering with separated differential and common-mode RC networks near the CSA pins. — Front-end filtering — differential RC near pins; slower common-mode RC

Sampling bandwidth

Rule: align conversion time and averaging to the step-load spectrum; capture both peak and settle regions.

Why: fast loads span tens of kHz to MHz; telemetry must not smear short OC spikes.

Pitfall: over-averaging masks fault signatures.

Sampling bandwidth and conversion time aligned to step-load spectra; store instantaneous plus averaged values. — Sampling windows — instantaneous and averaged capture

Power/Energy integration

Rule: define fixed windows (e.g., 1/10/100 ms) and overflow behavior; attach timestamps.

Why: consistent windows simplify field correlation and post-mortem analysis.

Pitfall: mixed window lengths make telemetry hard to compare across units.

Energy integration with fixed windows, register accumulation, overflow handling, and timestamps. — Energy integration — fixed windows, register accumulation, overflow handling, timestamps

Error Sources & Mitigation

Build the error budget from sensor to firmware; for each source apply a clear Rule → Why → Pitfall → Mitigation.

Amplifier offset & drift

Rule: budget input-referred offset/drift before gain.

Why: offset dominates small-current accuracy and scales with gain.

Pitfall: excessive gain multiplies offset into large code errors.

Mitigation: low-Vos parts; production trim at temperature; store calibration constants.

PGA gain error

Rule: include gain tolerance/tempcos in the slope term.

Why: PGA tolerance shifts current-per-LSB.

Pitfall: mixing PGA bins breaks fleet comparability.

Mitigation: device binning; per-board slope calibration; lock PGA per SKU.

ADC quantization & conversion time

Rule: ensure LSB ≤ required resolution; tune conversion time to capture peaks.

Why: coarse LSB and long averaging smear transient signatures.

Pitfall: over-averaging hides short OC spikes → late trips.

Mitigation: dual path: instantaneous + averaged; shorten conversion under protection modes.

Rshunt tolerance & TCR (self-heating)

Rule: choose low-TCR shunts and power-derate worst-case ambient.

Why: ΔR from TCR/self-heating skews slope across temperature.

Pitfall: hot spots near pads create gradient-induced drift.

Mitigation: 4-wire Kelvin; mirrored copper for heat spreading; temperature-cal tables.

PCB copper resistance & via imbalance

Rule: Kelvin pick-off from inner shunt pads; minimize series copper.

Why: parasitic resistance adds phantom current.

Pitfall: asymmetric routes inject CM → differential error.

Mitigation: symmetric pair, matched length, short return loop.

Kelvin failure (wiring/placement)

Rule: sense from inner pads; avoid shared load/rail copper.

Why: shared current paths corrupt the sense nodes.

Pitfall: passes DC checks but fails on load steps.

Mitigation: re-probe at pads; audit vias with X-ray; enforce keep-outs.

Firmware & telemetry handling

Rule: store slope/offset per board; time-stamp alerts; use moving average for reporting only.

Why: separates fast protection from slow telemetry.

Pitfall: protection based on averaged values is sluggish.

Error-budget waterfall: offset/drift, PGA gain error, ADC LSB, Rshunt tolerance/TCR, copper parasitics. — Error-budget waterfall — major contributors across the chain

Kelvin failure symptoms under load steps: phantom offset, polarity flip, inconsistent readings. — Kelvin failure — symptoms vs correct Kelvin pickup

Production calibration matrix: slope/offset at two temperatures, per-board constants and bins. — Calibration matrix — per-board slope/offset at two temperatures

Layout & Kelvin Routing

Four-wire Kelvin connection

Rule: pick up from the inner shunt pads.

Why: eliminates drop across load/rail copper.

Pitfall: vias outside pads include IR drop; use short direct routes into CSA pins.

Differential symmetry & return path

Rule: route a tight, symmetric differential pair from pads to CSA.

Why: cancels common-mode pickup and reduces loop area.

Pitfall: asymmetry and detours across high di/dt zones inject errors.

Avoid high di/dt zones

Rule: keep the sense pair away from switch nodes, inductor fringing, and hot copper.

Why: reduces injected CM and thermal gradients.

Pitfall: crossing SW nodes or gate-drive paths creates spikes and ringing in measurements.

Filter placement vs CSA

Rule: place the differential RC at the CSA pins; common-mode RC slower (5–10×); TVS/ESD near connector/rail.

Why: preserves signal integrity while improving EMI/ESD robustness.

Pitfall: long stubs between RC and pins can resonate; keep stub < 5 mm.

Single-point ground reference

Rule: star-connect the CSA reference to the measurement ground, not power ground pour.

Why: prevents ground-bounce from modulating the measurement.

Pitfall: multiple returns create loops and offset shifts.

Thermal spreading & copper design

Rule: heatsink the shunt with balanced copper; mirror pours around pads.

Why: reduces temperature gradient (TCR error) across the shunt.

Pitfall: asymmetric pours near hot parts cause drift with load.

DFM notes

Rule: lock footprint (pad chamfer, mask openings) per shunt vendor; verify via-in-pad rules.

Why: reflow variations change effective resistance and solder geometry.

Pitfall: cross-lot changes shift measurements if not controlled by SPC.

Kelvin four-wire pickup from inner shunt pads with symmetric differential routing to CSA pins. — Kelvin four-wire — inner pads to CSA pins with symmetric routing

Layout do’s and don’ts: avoid high di/dt, keep differential symmetry, short RC at CSA pins, single-point ground. — Layout do’s & don’ts — symmetry, RC at pins, avoid high di/dt

Thermal spreading around Rshunt: balanced copper to minimize temperature gradient and TCR error. — Thermal design — balanced copper to reduce temperature gradient

Protections & Thresholds

Configure the protection stack to react fast to faults while avoiding nuisance trips. Define, per fault, the trio Trip / Hysteresis / Delay, and coordinate the CSA/monitor with eFuse/Hot-Swap/Load-Switch for fast trips.

Fault types & responses

Over-current (OC): sustained overload above limit. Rule: Trip slightly above worst inrush/AVP peak and add hysteresis. Pitfall: setting Trip too tight causes false trips on step loads.
Short-circuit (SC): rapid, very high current. Rule: use a fast comparator/ALERT path (bypass slow averaging) and apply blanking. Pitfall: relying on averaged telemetry delays protection.
Reverse/Backfeed: current into a disabled/lower rail. Rule: enable reverse-current detection or sign-bit logic and trip reverse-block in the eFuse. Pitfall: ignoring negative polarity misses the event.

Foldback & transient suppression

Foldback: above thermal or droop thresholds, reduce the current setpoint vs VOUT/temperature to keep the rail alive.

TVS/RC: use RC to tame dv/dt across the sense input and TVS at connectors; size RC to avoid phase lag at threshold.

Threshold programming

Trip: ~1.1–1.3× max normal peak.
Hysteresis: ~5–15% of Trip to prevent chatter.
Delay: fast path 1–10 us; normal path 100–500 us.
Latch vs auto-recovery: SC = latched (manual clear); OC = auto-recovery with retry counter.

Protection map: OC/SC/backfeed detection with Trip/Hysteresis/Delay and foldback paths. — Protection map — OC, SC, backfeed, foldback, and threshold trio

ALERT/PG wiring to eFuse/Hot-Swap for fast trip; MCU reads PMBus for logging. — Fast path — ALERT/PG into eFuse/Hot-Swap; MCU logs via PMBus

Threshold tuning: trip window vs inrush/AVP peaks; hysteresis and delay settings. — Threshold tuning — trip vs inrush/AVP peaks; hysteresis and delay

Telemetry & PMBus Registers

Core registers

Shunt Voltage — differential sense across Rshunt.
Bus Voltage — rail sampler for P = Vbus × I.
Current — computed from Vshunt and slope.
Power — instantaneous and averaged power codes.
Alert Limit — per-fault limits (OC/SC/backfeed).
Mask/Enable — enable bits per alert source.
Status — sticky flags and overflow bits.

Register map: Shunt/Bus/Current/Power plus Alert Limit, Mask/Enable, and Status. — Register map — measurement and alert/control registers

Sampling configuration

Conversion time per channel (Vshunt/Vbus).
Averaging count (e.g., 1/4/16/64).
Alert queue/debounce (e.g., 1/2/4 samples).
Rule: run a dual path — instant (no averaging) for protection and averaged for reporting.

Sampling modes: instantaneous path for protection and averaged path for reporting. — Sampling modes — instant protection path and averaged reporting path

Calibration workflow

LSB/Cal registers: program Current_LSB (A/LSB) from Rshunt & gain; write slope/offset.
Procedure: measure two points (near-zero & mid-range) at two temperatures; compute slope/offset; write; read-back verify.
Traceability: store per-board constants (version & checksum) in EEPROM/flash.

Calibration flow: compute LSB and slope/offset; write Cal registers; read-back verify; store per-board constants. — Calibration flow — from LSB to per-board constants

Black-box telemetry

Timestamped events: Trip/Clear, snapshots of I/Vbus/Power, overflow markers.
Fixed windows: 1/10/100 ms power windows for fleet comparability.
Export: periodic CSV/diagnostic dump for field service.

Black-box logging with timestamps, threshold crossings, overflow handling, and fixed power windows. — Black-box telemetry — timestamps, threshold crossings, overflow and windows

Validation & Test Plan

Static: zero/mid/full-scale vs temperature

Temperature sweep from −40 to +125 °C at steps (e.g., −40/−20/0/25/60/85/105/125 °C). At each point, measure zero, mid, and full-scale current with logs: Vshunt, Vbus, Current, Power, device Temp, PGA, conversion time, averaging, timestamp.

Outputs: per-temperature slope/offset, drift (ppm/°C), and residual error.

Static validation matrix across temperatures with zero, mid, and full-scale points. — Static validation matrix — temperature vs zero/mid/full-scale points

Dynamic: step, surge/short, reverse/backfeed

Step load: define amplitude and slew (A/us), duty/period; measure latency to ALERT, overshoot/undershoot, recovery time.
Surge/Short-circuit: define source impedance and loop inductance; apply blanking; verify fast-trip timing.
Reverse/Backfeed: inject negative current into a disabled/lower rail; confirm detect and reverse-block.

Dynamic step-load — latency, overshoot/undershoot, recovery

Quantification: error budget & repeatability

Error budget: list contributors (Vos/drift, PGA gain error, ADC LSB, Rshunt tolerance/TCR, copper parasitics); compute RSS and worst-case; compare with spec.

Consistency & repeatability: N=10 boards, 3 runs each; report mean/standard deviation and R&R index.

Error budget comparison: RSS versus worst-case across offset, gain, ADC LSB, Rshunt, and copper. — Error budget — RSS vs worst-case contributors

Documentation artifacts

Measurement logs (CSV): fields with units for each run.
Calibration file: slope/offset at two temperatures with version and checksum.
Register export (CSV): per-run dumps for traceability.
Plots/report: derived charts and summary for release.

Documentation flow: measurement logs, calibration files, and register CSV exports. — Documentation flow — logs, calibration, register CSV exports

IC Selection — 7 Brands

Legend for the IC selection matrix: fields and abbreviations. — Legend — fields: Brand, Family/PN, VCM, Gain/PGA, I Range, ADC/Resolution, I2C/PMBus, Alerts, Package, AEC-Q100, Notes

Brand | Family/PN: TI | INA240-Q1

VCM Range: -0.3 to 80 V Gain/PGA: 20/50/100/200 V/V ADC/Resolution: Ext ADC (12–16 bit typical)

I Range (via Rshunt): depends on shunt; bidirectional supported I2C/PMBus: SMBus-compatible (via companion monitor)

Alerts: Fast comparator/ALERT (via monitor) Package: TSSOP/SOIC AEC-Q100: Yes

Notes: Zero-drift architecture; strong CMRR for PWM environments.

Brand | Family/PN: ST | TSC2020-Q1

VCM Range: 0 to 70 V Gain/PGA: 20/50/100/200 V/V ADC/Resolution: Integrated 16-bit monitor

I Range (via Rshunt): per Rshunt sizing; bidirectional I2C/PMBus: I2C/SMBus

Alerts: OC/OV/UV comparators Package: TSSOP/QFN AEC-Q100: Yes

Notes: Integrated shunt/bus voltage sense; automotive qualified.

Card-style layout preview for IC rows; mobile-friendly stacked fields. — Card layout — each IC is a self-contained row with consistent fields

Seven-brand scope — TI, ST, NXP, Renesas, onsemi, Microchip, Melexis

Application Recipes

Drop-in starting points for four common scenarios. Each recipe gives a quick Rshunt estimate, PGA setting, RC filters, and initial thresholds, plus notes for alerts/firmware coupling. Adjust with lab data from your platform and migrate the parameters into production.

VRM rail monitoring (with AVP/load-line)

High-speed transients; needs fast OC/SC and AVP-aware thresholds.

Rshunt estimate: 20–50 mV at Imax. Example: 60 A → 0.5–0.83 mΩ.
PGA: 20–50 V/V (keep headroom vs input swing).
RC filters: diff RC fc ~ 100–200 kHz; CM RC ~ 10–30 kHz.
Initial thresholds: OC Trip ≈ 1.15× normal peak; Hyst 10%; Delay_fast 2–5 µs; SC latched.
Notes: tie ALERT to phase-gain boost; log instantaneous + 1/10 ms power windows.

VRM monitoring with AVP/load-line: shunt, CSA, thresholds, and phase gain boost via ALERT. — VRM/AVP — shunt to CSA to thresholds to phase gain boost

Battery / USB-PD port (bidirectional, eFuse-linked)

Charge/discharge metering and port current limiting with reverse protection.

Rshunt estimate: 10–25 mV at Ilimit. Example: 5 A → 2–5 mΩ.
PGA: 50–100 V/V; verify wide VCM for PD rails (to ~20–24 V).
RC filters: diff RC fc ~ 5–50 kHz; CM RC ~ 1–10 kHz; TVS near connector.
Initial thresholds: OC Trip = Ilimit (e.g., 5.1–5.5 A), Hyst 8–12%, Delay_norm 100–300 µs; Reverse trip on persistent negative sign.
Notes: ALERT → eFuse fast trip; PMBus logs for black-box.

USB-PD/battery high-side bidirectional sensing with eFuse fast-trip and reverse detection. — USB-PD/Battery — bidirectional sensing with eFuse fast trip

Motor / heater load (short/locked-rotor, foldback)

Manage inrush and stall currents; protect with fast SC trip and foldback.

Rshunt estimate: 25–50 mV at rated current; confirm power rating and TCR.
PGA: 20–50 V/V; lower gain if stall peaks are large.
RC filters: diff RC fc ~ 10–100 kHz; CM RC ~ 2–20 kHz.
Initial thresholds: SC Trip ≈ 2–4× rated I (latched, 1–3 µs); OC Trip ≈ 1.2× rated I (auto-retry).
Notes: ALERT → load switch/eFuse; log thermal for TCR correlation.

Motor/heater recipe: stall/short detection, foldback strategy, RC placement. — Motor/Heater — short/locked-rotor detection and foldback

Server / networking (multi-rail aggregation)

Unify telemetry across many rails and align timestamps for system analytics.

Rshunt estimate: per-rail class: VRM-like (core) or battery-like (12 V aux) targets.
PGA: common settings per rail group to simplify calibration.
RC filters: keep diff RC consistent per group; CM RC tuned by chassis EMI.
Initial thresholds: rail-specific OC with alert queue 2–4 samples; power windows 1/10/100 ms.
Notes: Telemetry Hub aligns timestamps; PG voters aggregate fault lines.

Server/networking: multi-rail aggregation with Telemetry Hub and timestamp alignment. — Server/Networking — multi-rail aggregation and timestamp alignment

Parameter quick picks (start values)

Use these as initial targets; refine with lab measurements from your platform.

Parameter quick picks: Rshunt estimate, PGA, RC cutoff, and initial thresholds per recipe. — Quick picks — Rshunt, PGA, RC cutoffs, and initial thresholds by recipe

FAQs

1) Low-side vs high-side — when to choose?

Rule: low-side for simple, low-VCM rails; high-side for true load current and reverse protection.

Why: low-side adds ground lift; high-side sees real load current independent of return wiring.

How to set: check VCM range, input swing, and common-mode rejection vs your rail.

Pitfall: low-side can break PG thresholds; high-side needs wide VCM and fast alert paths.

2) How to remain linear and stable from 0 to 60 V common-mode?

Rule: select CSA/monitor with VCM headroom beyond your max bus and verify input swing vs PGA.

Why: input clamps and stage headroom set linearity and overdrive recovery.

How to set: choose PGA so Vshunt*gain stays inside input swing; validate with step loads.

Pitfall: hidden clamp activation under pulses leads to code compression.

3) RC filters for pulsed loads — how to avoid masking transients?

Rule: split filters: fast differential RC at CSA pins; slower common-mode RC 5–10x lower bandwidth.

Why: preserves edge information while taming CM injection and EMI.

How to set: pick fc based on edge content (VRM 100–200 kHz; battery 5–50 kHz; motor 10–100 kHz).

Pitfall: RC too slow hides SC edges; too fast raises noise and false trips.

4) Bidirectional zero-bias — how to calibrate and compensate drift?

Rule: set mid-scale offset and store slope/offset per board with temp coefficients.

Why: zero-drift parts still have temp/hysteresis; offset dominates low-current error.

How to set: two-point, two-temperature calibration; write registers; read-back verify; log constants.

Pitfall: using room-temp offsets only causes cold/hot bias.

5) How big should Rshunt be to keep efficiency yet ensure resolution?

Rule: budget 10–50 mV drop at max current; derate power and TCR.

Why: more drop increases resolution but wastes power and heats the shunt.

How to set: R = Vshunt_max / Imax; choose low-TCR and right footprint for self-heating.

Pitfall: asymmetric copper near pads adds gradient drift.

6) INA/CSA bandwidth vs noise — how to trade?

Rule: use the lowest gain that meets resolution; bandwidth just enough to capture needed edges.

Why: higher gain amplifies offset and noise; excessive BW adds noise.

How to set: align BW with protection edge content; rely on averaging for reporting only.

Pitfall: averaging in protection path delays trips.

7) Over-current limits — how to avoid tripping on normal inrush?

Rule: set Trip ~1.1–1.3x normal peak; Hyst 5–15%; Delay_fast 1–10 us.

Why: distinguishes transients from faults.

How to set: use dual path: instant comparator for protection; averaged path for telemetry.

Pitfall: zero hysteresis causes ALERT chatter.

8) Coordinating timing with eFuse/Hot-Swap for fast trips?

Rule: wire ALERT/PG directly to fast-trip pins; MCU supervises and logs.

Why: hardware path reacts in microseconds; firmware is slower.

How to set: strong pull-up, short trace; apply blanking to ignore switch bounce.

Pitfall: weak pull-ups slow the edge, delaying trips.

9) PMBus Alert Queue — how to prevent chatter?

Rule: set queue to require 2–4 consecutive samples before asserting ALERT.

Why: filters out narrow noise spikes.

How to set: start with queue=2; raise to 4 if environment is noisy.

Pitfall: too large a queue delays protection events.

10) Production calibration — recommended flow & traceability?

Rule: two-point calibration at two temperatures; store constants per board with checksum.

Why: captures offset and slope drift.

How to set: write LSB/Cal registers; read-back; log versioned files.

Pitfall: mixing bins or unlogged rework breaks fleet comparability.

11) Kelvin failure — typical symptoms & quick triage?

Rule: always probe at the inner shunt pads; compare readings to node points.

Why: shared current paths corrupt sense nodes.

How to set: inspect via symmetry and keep-outs; re-route if asymmetry exists.

Pitfall: passes DC test but fails under load steps.

12) Energy integration & logging — for field forensics?

Rule: integrate power in fixed windows (1/10/100 ms) and timestamp events.

Why: standard windows make fleet data comparable.

How to set: rolling accumulation with overflow markers; periodic CSV dumps.

Pitfall: variable windows make correlation hard across units.

13) AEC-Q100 scenarios — what extra tests?

Rule: add ESD/EMC, temp cycling/HTOL, vibration/shock, salt/mist, and latch-up checks.

Why: automotive reliability and environmental robustness.

How to set: align with OEM test plans; log serial and lot IDs.

Pitfall: neglecting PCB-level stress can pass IC-level but fail system-level.

14) Multi-rail aggregation — reference/ground loops & crosstalk?

Rule: star-reference measurement ground; keep differential pair symmetry and guard near aggressors.

Why: avoids ground loops and CM to differential conversion.

How to set: spacing/guard traces; avoid crossing switch nodes.

Pitfall: shared return with power devices injects switching noise.

15) High-temperature self-heating — how to control zero-drift from Rshunt?

Rule: select low-TCR shunts, derate power, and mirror copper around pads.

Why: temperature delta across the shunt biases the slope.

How to set: symmetric copper, thermal relief planning; add temp-comp tables if needed.

Pitfall: large copper on one side only creates drift with load.

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Current Sense Amplifiers & Shunt Monitors