Electronic Circuit Protectors & Power-Switch Controllers: eFuse, Hot-Swap, ORing, Mux

Choose by VIN (5 / 12 / 24 / 48–60 V)

5–20 V rails often favor eFuse or Load Switch; 48–60 V telecom/server usually needs a Hot-Swap Controller (controller+FET with SOA headroom).

Need reverse blocking?

Choose Back-to-Back FET or Ideal-Diode ORing for true reverse isolation and low forward drop.

Hot-plug & high surge?

For line cards and harsh plug-in events, use a Hot-Swap Controller; industrial 24 V may also qualify with robust eFuse + proper SOA check.

Low RON small handheld?

Prioritize Load Switch (low R_ON, soft-start). Verify reverse leakage and dV/dt ramp to avoid nuisance trips.

Dual source?

Use a Power-Mux for priority and seamless switchover; combine with ideal-diode behavior for redundancy.

eFuse (integrated FET) vs Controller + External FET

eFuse integrates FET + protection in a compact device. Controller + external FET trades size for lower R_DS(on) and higher SOA headroom under short events.

• Use when: 5–24 V compact rails (eFuse) or higher current/efficiency (Controller+FET).
• Watch-outs: eFuse thermal limits; external FET SOA sizing + copper spreading.

Hot-Swap Controllers (48–60 V, line cards, timing & surge)

Controls inrush during plug-in, limits current, and sequences power-good—common in telecom/server backplanes.

• Use when: 48–60 V, hot-plug, long supply harness, strict PG/FLT timing.
• Watch-outs: short-circuit energy, blanking/deglitch setup, TVS & surge coordination.

Load Switch (low R_ON handheld; inrush ramps; reverse blocking)

Low-loss power gating for 3–20 V rails with soft-start and basic protections—ideal for SoC and module branches.

• Use when: small devices, low R_ON, sequencing many rails.
• Watch-outs: dV/dt to avoid false trips; confirm reverse-blocking/leakage needs.

Ideal-Diode ORing (B2B FET, drop & backfeed behavior)

FETs emulate a low-drop diode for redundancy and true reverse isolation; often uses back-to-back FETs.

• Use when: dual sources, low forward drop, strict backfeed control.
• Watch-outs: expected forward drop, reverse-current threshold, EMI during switchover.

Power-Mux (priority, seamless switchover; diode-OR vs controller mux)

Selects between two sources by priority/health; can achieve seamless switchover and pair with ideal-diode behavior.

• Use when: adapter/battery dual-source, industrial main/backup.
• Watch-outs: switchover transients, PG/FLT coordination with supervisors.

Analog thresholds vs I²C / PMBus programmable

Fixed-threshold analog parts minimize cost/complexity; programmable parts add telemetry, field policy tuning, and logging.

• Choose PMBus/I²C for remote control, margining, and diagnostics.
• Align fault policy (latch vs auto-retry) with system watchdog and safety goals.

ILIMIT — internal vs. Rsense; tolerance; foldback (CC/FB)

Sets short-event energy and thermal stress.

Measure: pulse load + surge; verify CC vs foldback curve and tolerance; pair with proper blanking. See validation

Inrush / dV/dt — ramp, C_load, surge rating

Startup spikes are the #1 cause of nuisance trips.

Measure: record Vout slope & I_inrush peak; leave margin to ILIMIT. See layout tips

Trip timing — blanking/deglitch; latch vs auto-retry

Separates true faults from harmless spikes.

Latch vs auto-retry: prevent oscillation with proper backoff and system watchdog. See timing waveforms

R_ON / R_DS(ON) & Thermal rise — I²R + θ_JA/θ_JC; OTP

Controls steady loss and junction temperature.

Measure: steady-state ΔT and hotspot map; ensure OTP margin at worst VIN and ambient. See thermal layout

UVLO / OVP windows; accuracy; PG/FLT signaling

Defines power boundaries and system handshake.

Measure: slow sweep with ripple injection; verify PG/FLT edges and debounce. See bring-up checks

Reverse current thresholds; ideal-diode forward drop

Critical for backfeed control and redundancy.

Measure: reverse injection test; observe switchover EMI and any oscillation. See integration

ESD / Surge — quick notes

Pre-compliance discipline saves time later.

• TVS selection & placement close to entry; shortest return loop.
• Ground partitioning; snubbers or RC damping if needed.
• Run IEC 61000-4-2/4/5 pre-checks; watch for FLT chatter.

Surge/EFT on long cables; fast short-to-GND isolation; clean UV/OV windows for PLC backplanes.

Reverse-battery, cold-crank, load-dump; parts should meet AEC-Q100 with PPAP when required.

Hot-swap on line cards; ORing for redundancy; pay attention to SOA sizing and short-event energy.

Role swap and BC1.2 behaviors; fast reverse-blocking and controlled dV/dt protect downstream loads.

Low R_ON power gating to display/SoC rails; tight inrush control to avoid brown-outs.

Strict compliance boundaries; derating and documentation beyond commercial norms.

ILIMIT / Rsense

Rsense ≈ Vthr / Ilimit. Include tolerance & temperature drift.

Inrush ramp (dV/dt)

Iinrush ≈ Cload · dV/dt. Pick dV/dt from the chosen ILIMIT, then verify surge.

SOA check (external FET under short-to-GND)

Approximate worst short as a V–I–t rectangle and compare with the device SOA curve.

Thermal rise (ΔT)

ΔT ≈ I² · R_ON · θ_JA. Include pad, vias, copper spread, enclosure.

Trip timing (blanking vs actual fault; avoid oscillation)

Set Tblank above benign transients but below dangerous energy. Add backoff to stop auto-retry heating.

• Kelvin sense for shunts / internal sense pins; route as a pair, keep away from high di/dt nodes.
• PG/FLT lines as logic nets: reference ground, add RC if needed, keep away from switch nodes and long antennas.
• Thermal vias under the FET pad; wide copper spread on inner/outer layers；stitch shields around hot areas.
• TVS at entry (connector side) with shortest return; add RC snubbers where ringing shows up.
• Back-to-back FET orientation arrows to clarify reverse blocking; mark silk for probe points.

• Don’t share sense with power return; don’t cross switch node; avoid via forests on sense.
• Don’t run PG/FLT parallel to fast gate or inductor edges; avoid high-impedance stubs.
• Don’t leave FET pads without vias/copper; avoid thermal bottlenecks near connectors.
• Don’t place TVS far from entry; long traces kill its effectiveness.
• Don’t flip B2B FET order; mis-orientation breaks reverse blocking and increases leakage.

Connect with no capacitive load. Power on with nominal VIN.

Attach worst-case C_load (± tolerance and cable inductance)。Bring up and capture peak I_inrush.

• Pass: I_inrush < 0.8 × I_LIMIT; PG clean; no FLT.
• Fail: Inrush hits limit or causes PG/FLT chatter → lower dV/dt or raise limit with SOA review.

See dV/dt guidance

Use controlled short. Capture trip timing and current profile (CC or foldback). Log case/J temperature spike.

Inject reverse voltage/current to the load path; observe ideal-diode behavior and isolation.

• Pass: Backfeed < threshold; correct B2B FET orientation; no self-oscillation.
• Pitfall: Gate discharge or body-diode path causing leakage.

Run IEC 61000-4-2/4/5 pre-compliance. Place TVS at entry with shortest return.

• Pass: No damage; function continues; PG/FLT recovers stable.
• Pitfall: Distant TVS or long ground loops reduce clamping effectiveness.

Close the lid. Measure ΔT at hotspot/case/ambient under worst VIN and duty profile.

• Pass: ΔT < project limit (e.g., 50–60 °C) with >10 °C margin to OTP.
• Pitfall: Single-point reading hides hotspots—use IR map.

Characterize Tblank, Ttrip, Tretry. Ensure thermal cooldown and system watchdog policy align.

• Pass: No thermal ratcheting; retry interval ≥ 5× thermal time-constant.
• Pitfall: Backoff too short; unstable load causes chatter.

UL / IEC context (e.g., IEC 62368-1 usage)

Automotive — AEC-Q100 grades; ISO 16750 transients

EMC — IEC 61000-4-2 (ESD), -4 (EFT), -5 (Surge)

USB-IF notes — power path / role swap

Document set — CoC, PPAP, RoHS/REACH

Set C_load and target dV/dt, check I_inrush vs. ILIMIT margin.

Rsense ≈ V_thr / ILIMIT; includes tolerance & temperature drift tables.

V·I·t rectangle vs. SOA; ΔT ≈ I²·R_ON·θ_JA; board-level heat paths.

Step-by-step bring-up: scope channels, thresholds, pass/fail windows, and logs.

Architecture × VIN buckets with flags for reverse-block, telemetry, low R_ON, and AEC-Q100.

eFuse vs. hot-swap—when to choose which?

Use eFuse for 5–24 V rails with integrated FETs, compact footprints, and moderate surge. Choose hot-swap controllers for 24–60 V backplanes, plug-in cards, and large inrush where external FET SOA is sized. If redundancy is required, pair with ORing. Learn more in Architectures.

How do I prevent inrush from false-tripping OCP?

Set dV/dt to keep I_inrush below ~80% of ILIMIT, add blanking/deglitch on OCP, and account for C_load tolerance and cable inductance. Verify with scope: VOUT ramp, inrush peak, PG stability. See Parameter Playbook and formulas in Design Calculations.

Do I always need back-to-back FETs for reverse block?

Not always. For simple non-critical paths, body-diode aware eFuses may suffice. For true isolation, seamless switchover, or ORing, use back-to-back FETs or ideal-diode controllers. Confirm leakage/backfeed limits and orientation arrows on layout. See Topologies and Layout.

Auto-retry oscillation—common causes and cures?

Too-short retry backoff, capacitive loads that partially recharge, or thermal time constants cause oscillation. Increase retry interval, adjust dV/dt, or switch to latch mode for critical rails. Validate with temperature and current waveforms. Details in Validation and Timing trade-offs.

USB-PD role swap—how to avoid backfeed risks?

Use controllers supporting fast reverse blocking and coordinate CC negotiation with power-path timing. Verify VBUS switchover transients, ideal-diode thresholds, and PG/FLT behavior during swap. Test legacy BC1.2 interactions. See Applications and Power-mux/ORing.

Telemetry vs. analog monitoring—worth it?

Telemetry (I²C/PMBus) adds visibility for trend and fleet data, while fast protection remains local. It’s valuable for high-reliability systems and field diagnostics; ensure scaling alignment and alert coalescing. For minimal BOM, analog PG/FLT may suffice. Integration tips in PMIC/PMBus Integration.

AEC-Q100 vs. commercial—what really changes?

Automotive parts add grade-specific temperature, reliability stress, lot controls, and documentation (e.g., PPAP). Behavior may also differ in ESD/Surge robustness or diagnostic features. Verify grade, derating, and compliance evidence. See Standards & Compliance.

How much ILIMIT margin is enough?

Start with peak steady load ×1.25–1.5×, then check inrush and worst-case tolerance/temperature. Ensure foldback/CC curves align with load behavior. Validate against trip blanking and retry policy. Calculations in Design, trade-offs in Parameters.

SOA check with external FET—fastest method?

Approximate with a V·I·t rectangle using measured short-event waveforms, then compare to SOA at the right pulse width and temperature. Add derating for board heating and repetitive events. Bench steps in Validation; formulas in Design.

Load switch or eFuse for low-RON handheld rails?

Prefer load switches for ultra-low R_ON, tiny packages, and simple sequencing. Choose eFuses when you need precise ILIMIT/UV/OV, reverse blocking, or telemetry. Confirm inrush dV/dt and backfeed needs. Compare in Architectures and Applications.

Ideal-diode ORing vs. controller-based power-mux?

Ideal-diode ORing excels at redundancy and low drop; it won’t arbitrate priority. Controller power-mux adds source preference, seamless switchover, and reverse blocking control. Pick based on source behavior and latency needs. See Topologies and Matrix.

Where should TVS go—entry or local to the IC?

Place the primary TVS at the connector/entry with the shortest return path. Add local RC/snubbers if the IC sees fast edges. Route PG/FLT away from noisy nodes and use Kelvin sensing. Guidance in Layout & EMC and Standards.

PG/FLT chatter—debounce at device or aggregator?

Debounce at the aggregator (supervisor/PMIC) so multiple rails share a consistent window. Keep leaf PG/FLT fast to reflect true faults. Use open-drain wired-AND and verify chatter against margining steps. See Integration and tests in Validation.

Do integrated-FET eFuses handle 48–60 V line cards well?

Some do for moderate current, but large surge and short-event energy often demand hot-swap controllers with external FETs sized for SOA. Validate plug-in surges, PG timing, and thermal rise. Selection guidance in Applications and the Compare Matrix.

ILIMIT

The maximum output current allowed before protection acts (trip or regulation). Set via internal reference or sense resistor; consider tolerance and temperature drift. Size margins so inrush stays <~80% of ILIMIT and steady peaks don’t nuisance-trip.

Foldback (FB)

A current-limit profile that reduces allowable current as VOUT collapses during a fault, lowering device power and aiding SOA. It protects silicon better than constant-current but may starve loads that need high start-up torque or hold-up.

SOA (Safe Operating Area)

The device-survivable region of voltage, current, and time. Compare your measured short-event V·I·t “rectangle” to the SOA curve at the correct pulse-width and temperature; add margin for repetition and board heating.

Latch / Auto-retry

Fault policies. Latch holds the output off until reset—safer for critical rails. Auto-retry periodically re-enables after a fault—good for recoverable loads but can oscillate if backoff is short or loads are highly capacitive.

UVLO / OVP

UVLO prevents operation below a safe voltage; OVP turns off or clamps above a limit. Window accuracy, hysteresis, and PG thresholds drive stability during hot-plug, margining, and brownouts.

PG / FLT

Power-Good (PG) signals a valid rail; Fault (FLT) indicates protection action. Open-drain or push-pull with vendor-specific polarity and delays. For multi-rail systems, debounce at the aggregator and keep leaf signaling fast.

B2B FET (Back-to-Back)

Two series MOSFETs with sources tied to block reverse current in both directions while keeping forward drop low. Core to ORing and power-mux paths; orientation arrows on layout help prevent accidental backfeed.

Ideal-diode

A controller that drives a MOSFET to emulate a diode with very low forward loss and fast reverse blocking. Enables redundancy ORing and seamless switchover without the heat of Schottky diodes.

dV/dt (Inrush ramp)

Output slew rate during start-up. Inrush ≈ C_load × dV/dt, so choose a ramp that keeps current below ILIMIT with margin and avoids tripping upstream supplies. Verify with scope and adjust soft-start components or registers.

Backfeed

Unwanted reverse current from output to input or between sources, often through body diodes or poorly tuned ideal-diode thresholds. Prevent via B2B FETs, correct controller settings, and clear current-flow orientation on the PCB.

PMBus

A digital power-management protocol (over I²C/SMBus) for configuration, telemetry, and fault reporting. Keep fast protection local in hardware; use PMBus to log events, poll slow trends, and coordinate system-level policy with the PMIC.