Solid-State & Photorelay ICs — Selection, Specs, and Use Cases

Overview image showing photorelay internal structure with LED input, photovoltaic driver, and back-to-back MOSFET output. — Photorelay / Solid-State Relay at a glance — the input LED drives a photovoltaic stage; the output uses back-to-back MOSFETs for AC-capable isolation.

This page explains solid-state relays (SSR) and photorelay ICs from an engineer’s perspective. Replacing mechanical contacts with an LED + photovoltaic driver + MOSFET output brings lower leakage, no contact bounce, and long life. We focus on actionable parameters — R_ON, I_LEAK, C_OFF, t_ON/t_OFF, V_ISO, and dv/dt immunity — compare against mechanical/reed/triac SSRs, and provide a selection flow, mini application diagrams, compliance checklist, cross-references, and an RFQ entry.

Who is this for?

Instrumentation / ATE / medical projects needing ultra-low leakage & low C_OFF
Small-current, multi-channel switching in PLC I/O, telecom lines, security panels
Teams migrating from mechanical/reed/triac SSRs to MOSFET-output SSRs

What you’ll get

Comparison framework: mechanical / reed / triac SSR / MOSFET SSR
Selection flow: load → voltage/current → leakage/capacitance → safety
Design notes: I²·R_ON thermal, dv/dt immunity, RC snubber
Mini diagrams: ATE MUX, medical isolation, PLC I/O
Cross-references and small-batch RFQ path

R_ON: on-resistance → power & temperature rise I_LEAK: off-state leakage → bias on high-impedance nodes C_OFF: off-capacitance → crosstalk/bandwidth t_ON/t_OFF: speed/symmetry V_ISO: isolation rating / creepage dv/dt immunity: false turn-on & mitigation

Submit your BOM (48h) Start with the selection flow

1) Definition & Working Principle

A solid-state relay (SSR) is an isolation device that switches electrical loads without mechanical contacts. A photorelay (often called PhotoMOS) is a MOSFET-output SSR that uses an internal LED on the input side, and a light-sensitive driver on the isolated output side. Compared with mechanical or reed relays, photorelays offer no contact bounce, long lifetime, low leakage, and compact SMD packaging, and are well-suited to small-signal and low-to-moderate current applications.

MOSFET output: back-to-back MOSFETs for bidirectional conduction (AC) or a single MOSFET for unidirectional DC.
LED-based input isolation: input LED is galvanically isolated from the output side.
Target use cases: instrumentation, ATE multiplexing, medical signal isolation, PLC/telecom small-current switching.

Internal structure of a photorelay IC showing LED input, photovoltaic driver, and back-to-back MOSFET output. — Internal signal path: LED → light-sensitive (photovoltaic/gain) driver → MOSFET output (back-to-back for AC, single device for DC).

AC back-to-back MOSFET vs DC single MOSFET output topology in solid-state relays. — AC vs DC topology: back-to-back MOSFETs provide bidirectional blocking for AC; a single MOSFET serves unidirectional DC loads.

How it works

Input: a forward current through the LED generates light.
Isolated drive: a photovoltaic or gain stage converts light to a gate drive for the MOSFET stack.
Output: the MOSFET(s) switch the load; back-to-back devices enable bidirectional blocking for AC.

Key parameters (quick reference)

R_ON (on-resistance): sets conduction loss P ≈ I²·R_ON and temperature rise.

I_LEAK (off-state leakage): bias error on high-impedance/precision nodes.

C_OFF (off-capacitance): affects bandwidth and crosstalk in multiplexers.

V_LOAD (rating): maximum load voltage (mind surge and derating).

I_CONT / I_SURGE: continuous and surge current capability.

t_ON / t_OFF: switching speed and symmetry.

dv/dt immunity: resistance to false turn-on in noisy environments; may require RC snubbering.

V_ISO & creepage: isolation test rating vs. working voltage and layout clearances.

2) Comparison & Positioning

Comparison of mechanical, reed, triac SSR, MOSFET SSR, and DIY MOSFET+driver across key specs. — High-level view across technologies and the most relevant specs for system design.

Module A — Technology comparison (spec-by-spec)

Compare mechanical relays, reed relays, triac SSRs (optotriac + triac), MOSFET-output SSRs (photorelays), and DIY MOSFET + gate driver builds across the parameters designers actually trade off.

Technology	On-state (R_ON/drop)	Off-state leakage	Speed	Lifetime	Ripple / noise	dv/dt immunity	Size	EMI	AC / DC fit	Cost
Mechanical relay	Very low drop	≈0 (open contact)	Slow (ms-level)	Limited (mechanical wear)	Contact bounce	High immunity	Bulky (coil + contacts)	Coil transients	AC & DC	$–$$
Reed relay	Low drop	Very low	Medium	Better than mech.	No bounce, but magnetics	Good	Smaller than mech.	Low	AC & DC	$$
Triac SSR (optotriac + triac)	Voltage drop (triac)	Not MOSFET-style	Medium; often zero-cross	High (no contacts)	Mains ripple; zero-cross artifacts	dv/dt sensitive (snubber)	Compact	Mains EMI concerns	AC only	$$
MOSFET-output SSR (photorelay)	R_ON limited; scales with current	Low (nA–µA class)	Fast (sub-ms to ms)	Very high	Clean; no bounce	Good; watch C_OFF & snubbers	Very compact (SMD)	Low	AC (back-to-back) & DC	$$–$$$
DIY MOSFET + driver	Config-dependent (can be very low)	Design-dependent	Fast	High (no contacts)	Layout-dependent	Depends on gate control & snubbers	Small to medium (discrete BOM)	Layout-dependent	AC (with back-to-back) & DC	$–$$$

Module B — Suitability map (AC vs DC / small-signal)

AC loads (mains, heaters, lamps, motors)

Triac SSR for pure AC control; consider zero-cross variants to reduce EMI on resistive loads.
Watch dv/dt false triggering; add appropriate RC snubber / MOV for noisy mains or inductive loads.
For precision AC signal switching (rare), consider MOSFET back-to-back topologies for lower distortion.

DC & small-signal / instrumentation

Photorelay (MOSFET-output SSR) excels with low leakage and low C_OFF—ideal for ATE MUX and precision front-ends.
Check R_ON vs. current for thermal loss; parallel channels only with thermal and sharing analysis.
If cost or current headroom is critical, a DIY MOSFET + driver can be tuned, but validate isolation & safety.

Rule of thumb: use triac SSRs for straightforward AC power loads; use photorelays for DC or precision analog where leakage, capacitance, and linearity matter.

Go to selection flow Download checklist / RFQ

3) Selection & Constraints

Selection flow for photorelay/SSR from load type to safety approvals. — Start with the load and work down to safety, packaging, and substitution.

Module A — Selection flow (8 steps)

Load type: AC / DC / analog signal. Choose back-to-back MOSFETs for AC; single MOSFET for DC/analog.
Voltage & surge: confirm V_LOAD (nominal & transient). Add derating for spikes and over-voltage.
Current & thermal: size for I_CONT and I_SURGE. Estimate P ≈ I²·R_ON, then ΔT ≈ P·θ_JA.
Accuracy / leakage: limit I_LEAK and C_OFF for high-impedance or precision nodes (MUX, sensing).
Speed: check t_ON/t_OFF and rising/falling symmetry vs system timing & bandwidth.
dv/dt robustness: evaluate environment; plan RC snubbers/MOV and layout to prevent false turn-on.
Isolation & safety: verify V_ISO, working voltage, creepage/clearance; apply MOPP/MOOP for medical.
Package / channels / substitution: pick SOP/SSOP/VSON; 1/2/4 ch; ensure pin-compatible alternates (lifecycle ready).

Thermal quick check: if ΔT is tight, choose lower R_ON or improve θ_JA (copper area, vias, airflow).

Precision paths: prioritize low I_LEAK & low C_OFF; mind linearity for analog switching.

Noise immunity: high dv/dt → plan snubbers + keep short loops; route away from fast edges.

Ultra-low leakage

Target I_LEAK ≤ nA class and low C_OFF for high-impedance nodes (ATE, precision sensing, mux trees).

Prefer photorelays with nA-class leakage & low output capacitance
Guard rings & shield routing reduce bias error
Validate across temperature (leakage vs. T)

High voltage (200–600 V)

Choose higher V_LOAD grades; confirm creepage/clearance and dv/dt immunity.

Back-to-back MOSFETs for AC; single-ended for DC
Add RC snubber/MOV for inductive or noisy lines
Check surge and derating (mains transients)

High-speed switching (< 1 ms)

Tight t_ON/t_OFF with good symmetry; minimize C_OFF for bandwidth and settling.

Time with the actual load R/C (edge-rate can vary)
Mind charge injection and kickback on analog nodes
Consider zero-cross options for AC power SSRs

Low R_ON / mid current

Balance R_ON vs. thermal headroom; confirm I_SURGE for inrush.

P ≈ I²·R_ON → check ΔT = P·θ_JA
Parallel only with sharing analysis & layout symmetry
Use copper area/vias for heat spreading

Medical / compliance

Meet 2×MOPP when required; verify leakage limits, V_ISO, creepage, and documentation.

Confirm working voltage vs. test rating (not the same)
Observe creepage/clearance by pollution degree
Keep audit trail (CB/UL/VDE certificates)

See example applications Download checklist / RFQ

4) Design Notes

Module A — LED input drive

Choose the LED forward current I_F to meet turn-on time and CTR/drive requirements while protecting lifetime and thermals. Use a series resistor and account for supply tolerance and LED V_F spread.

Target I_F: pick a nominal (e.g., 3–10 mA typical for small photorelays) per datasheet timing vs. I_F.
Series resistor: R_LED ≈ (V_DRV,min − V_F,max)/I_F,nom. Verify worst cases: I_F,max = (V_DRV,max − V_F,min)/R_LED.
Lifetime/thermal: keep I_F within recommended continuous ratings; derate with temperature.
Drive topology: GPIO/open-drain with resistor is common; for tight timing use a small transistor driver to reduce edge variability.
EMC: add a small series resistor or RC at the input if very fast edges couple into the barrier.

Module B — Power & thermal

Estimate conduction loss and temperature rise, then validate with your board’s thermal path and ambient.

Conduction loss: P ≈ I² · R_ON

Temperature rise: ΔT ≈ P · θ_JA

Junction estimate: T_j ≈ T_amb + ΔT

Current (A)	R_ON (Ω)	P (W)	θ_JA (°C/W)	ΔT (°C)
0.2	0.30	0.012	90	1.08
0.5	0.15	0.0375	60	2.25
1.0	0.05	0.05	40	2.00

Parallel devices: only with thermal/electrical sharing analysis; match traces and copper to balance R and heat.
R_ON vs. temperature: expect R_ON to rise with T; re-check ΔT iteratively.
Board design: use copper area, thermal vias, and airflow where applicable.

Power loss and temperature-rise estimation for solid-state relays with I²R. — Thermal estimation workflow: P ≈ I²·R_ON; ΔT ≈ P·θ_JA; then verify T_j vs. limits.

Module C — dv/dt & RC snubbers

Fast edges can couple through the output capacitance and internal paths, causing false turn-on. Use RC snubbers and layout discipline to raise immunity.

Identify the source: switching node, cable transients, inductive loads.
Pick C first: choose a small C (e.g., tens to a few hundred nF) to shunt high-frequency content.
Set R for damping: R ≈ √(L/C) or start with 10–100 Ω and tune by scope for minimal overshoot and acceptable dissipation.
Check power: verify snubber power at worst-case dv/dt / frequency; ensure component voltage ratings.
Layout: keep snubber loop tight; route away from high-impedance nodes; add MOV/TVS for surge if needed.

dv/dt false turn-on mechanisms and RC snubber sizing hints. — False turn-on pathways and a practical RC-snubber tuning sequence.

Module D — AC / H-bridge topologies

Back-to-back MOSFETs (AC): bidirectional blocking and conduction; required for AC loads to control both polarities.
Single MOSFET (DC): unidirectional; verify body-diode orientation and any reverse-blocking needs.
H-bridge switching: coordinate timing (dead-time) to avoid cross-conduction; consider gate path discharge for fast turn-off.
Snubbers & protection: place per leg; add MOV/TVS on the supply or line as appropriate.

Explore application diagrams Download thermal worksheet (PDF)

5) Applications & Reference Designs

Photorelay in ATE analog multiplexer with low leakage and low C_OFF.

ATE / Instrumentation Analog MUX

Key metrics: ultra-low I_LEAK, low C_OFF, linearity, settling
4-wire measurement: separate force/sense paths; minimize series R and leakage
Shielding: guard rings, short return paths; control charge injection

Selection direction: photorelay with I_LEAK ≤ nA, C_OFF low, t_ON/t_OFF in sub-ms; small SMD (VSON/SSOP) for density.

Battery IR / Safety Test Matrix

Key metrics: mid current, P = I²·R_ON thermal, dv/dt control
Surge/inrush: verify I_SURGE, add snubber/MOV for switching spikes
Matrix density: watch aggregate heat; copper area + vias for spreading

Selection direction: low-R_ON photorelay (or discrete MOSFET + driver if current headroom dictates); validate θ_JA/ΔT; ensure reverse blocking if required.

Medical patient-side signal isolation with photorelay and MOPP considerations.

Medical Patient-Side Isolation (Low-Voltage Signals)

Key metrics: 2×MOPP, creepage/clearance, leakage current limits
Signal integrity: low I_LEAK / C_OFF to avoid bias and bandwidth issues
Documentation: maintain CB/UL/VDE files and working-voltage definitions

Selection direction: photorelay with medical-friendly isolation rating, long creepage package, nA-class leakage; confirm working voltage vs. test rating.

PLC I/O (Small-Current Switching)

Key metrics: surge/EMI robustness, switching speed, ESD tolerance
Protection: input/output series resistors, snubbers, TVS as needed
Reliability: lifetime at elevated ambient; check θ_JA on dense I/O cards

Selection direction: compact SMD photorelay with adequate V_LOAD, dv/dt immunity, and ESD robustness; consider multi-channel packages for density.

Telecom / Line Switching

Key metrics: low C_OFF for crosstalk; ESD protection; surge coordination with front-end
Bandwidth/linearity: verify distortion and insertion loss on the band of interest
Compliance: align with surge/ESD requirements (e.g., ITU/IEC as applicable)

Selection direction: low-capacitance photorelay; pair with proper ESD diodes and surge elements (GDT/MOV) per line standard; route with controlled impedance if needed.

Check cross-reference directions Download checklist / submit RFQ

6) Safety & Reliability

Creepage and clearance requirements for isolated photorelay packages. — Isolation geometry matters: creepage (surface path) and clearance (through air) must match your working-voltage and pollution degree.

Isolation metrics — how to read the datasheet

Dielectric withstand (e.g., Vrms/1 min): production test level across the barrier; not the allowable continuous working voltage.

Working voltage: the max continuous voltage permitted in service under the specified pollution degree/altitude; often far below the test voltage.

Impulse/surge rating: short-duration over-voltage capability; coordinate with MOV/TVS and line protection.

Creepage & clearance: package geometry and PCB layout must meet the target category (basic/reinforced) at your over-voltage category.

Spec	Meaning	Design use
Isolation test (e.g., 3.75 kVrms/1 min)	Factory hipot stress	Qualification reference; not continuous rating
Working voltage (basic/reinforced)	Continuous service voltage	Primary design constraint (choose by standard)
Impulse (kV) / surge	Short transient withstand	Coordinate with MOV/TVS; check clearance

Medical use — MOPP/MOOP and leakage limits

MOPP vs MOOP: patient protection (MOPP) has tighter creepage/clearance and insulation; may require two independent protection means (2×MOPP).
Leakage current: ensure patient leakage and touch current limits by design (component choices + layout + shielding).
Documentation: maintain CB/UL/VDE certificates; confirm working voltage definitions and test methods in your risk file.

Reliability — lifetime & environmental robustness

Lifetime: no mechanical wear; verify LED derating and junction temperature under worst case.

Thermal cycling: consider ΔT cycles from load profiles; validate solder joint reliability.

Moisture sensitivity (MSL): follow handling/bake per package rating before reflow.

Surge/ESD/EMC: size RC snubbers, MOV/TVS; meet system ESD and immunity levels with layout control.

Pre-design checklist (12 items)

Define working voltage, pollution degree, altitude; pick basic/reinforced accordingly.
Check creepage/clearance (package + PCB) meet the chosen category.
Confirm isolation test vs. working voltage—do not equate them.
Size surge/impulse protection (MOV/TVS/GDT) and verify ratings.
Plan dv/dt immunity: RC snubbers, return paths, shielding.
Verify leakage limits for precision/medical paths (I_LEAK & patient leakage).
Thermal design: compute P = I²·R_ON, ΔT = P·θ_JA; ensure T_j margin.
Account for R_ON(T) increase; re-iterate ΔT at elevated ambient.
ESD/EMC: device level + system level; component placement and loop minimization.
Manufacturing: observe MSL, reflow profile, bake/handling requirements.
Reliability plan: thermal-cycle, surge, and life tests representative of use case.
Compliance file: keep certificates (CB/UL/VDE), test reports, and risk assessment aligned.

Check cross-reference directions Download checklist / submit RFQ

7) Brands & Cross-Reference

Cross-reference matrix of major photorelay/SSR families by voltage, leakage, and package. — Family-level view — voltage class, leakage class, speed, packages, channel count, and AC (back-to-back) availability.

Module A — Brand / family matrix (by attributes)

Use this matrix to shortlist families before drilling into datasheets. Dimensions: V_LOAD class, leakage class, switching speed, package, channels (1/2/4), AC capability (back-to-back), and compact options (VSON/USON).

Brand / Family (examples)	V_LOAD class	Leakage class	Speed	Packages / size	Channels	AC (back-to-back)	Notes
Omron — G3VM	~60–600 V (family-dependent)	nA–µA classes	Fast (sub-ms→ms)	SOP, SSOP, VSON (compact)	1 / 2 / 4	Yes (family options)	Broad coverage; many pinouts
Panasonic — PhotoMOS	~30–350 V (series-dependent)	nA–µA classes (very low options)	Fast	SSOP, SOP, VSON	1 / 2	Yes (select series)	Instrumentation focus; low C_OFF SKUs
Toshiba — Photorelay families	~30–350 V (series-dependent)	nA–µA classes	Fast	SOP, SSOP, VSON/USON	1 / 2	Yes (select series)	Very compact packages
Vishay — Photomos/SSR families	Varies by family	µA and below (some nA)	Fast	SOP/SSOP	1 / 2	Select options	Check leakage vs temp curves
Littelfuse / IXYS — CPC series	~60–350 V (series-dependent)	Low µA / nA options	Fast	SOP/SSOP	1 / 2	Select options	Industrial bias; check surge ratings
Cosmo / Brightk / others	Varies	Varies	Varies	SOP/SSOP; some compact	1 / 2	Select options	Value-oriented; validate leakage & consistency

Module B — Pin / package cautions

Pin mapping: SMD pinouts vary even within a brand; verify input polarity marks and output orientation.
Spec re-check: for substitutions, re-validate C_OFF, R_ON, leakage vs. temperature, and θ_JA thermal margin.
AC options: ensure back-to-back MOSFET versions for AC; DC-only parts won’t block both polarities.
Compact packages: VSON/USON reduce parasitics but demand tighter reflow and MSL handling.
Land pattern: follow the exact recommended footprint; confirm stencil and paste ratio for small pads.

Module C — Lifecycle & substitution strategy

Status taxonomy: New / Active / NRND / EOL — monitor PCNs and plan redesign thresholds.

Drop-in candidates: keep at least two pin-compatible alternates per footprint and voltage class.

Validation plan: re-run leakage, R_ON, timing, dv/dt, and surge tests on alternates; include temperature corners.

Supply chain: prefer authorized channels; sample incoming lots for leakage/R_ON to catch drift.

Continue to packaging & manufacturing Download checklist / submit RFQ

8) Packaging / Shipping / Production

Common photorelay packages (SOP/SSOP/VSON) and land-pattern highlights. — Common packages for photorelays: SOP / SSOP / TSSOP / VSON / USON — footprint and heat paths drive reliability.

Package choices & land-pattern guidance

SOP / SSOP / TSSOP: easy to route and rework; generous pad sizes.

Thermal: spread heat via wider output pads and copper pours
Assembly: IPC-7351 nominal footprints are a good starting point

VSON / USON (micro-leadframe/QFN-like): smallest parasitics and area.

Stencil: reduce paste (e.g., 50–70%) with window panes to avoid float/tilt
Thermal: if exposed pad is present, tie to copper with via array

Footprint notes:

Follow vendor-recommended land pattern and courtyard
Keep solder mask defined pads for fine-pitch VSON/USON when advised
Add copper keep-outs near isolation barrier if specified

MSL handling & reflow profile (key points)

MSL level: check the datasheet/label (typical MSL 3–5 for small QFN-like parts). Store in dry pack; log floor life after bag open.
Bake conditions: if floor life expires or humidity indicator card shows excursion, bake per package MSL before reflow.
Lead-free reflow: peak per spec (e.g., ≤260 °C max), time-above-liquidus and ramp rates per vendor curve.
Warpage/voids: for VSON/USON, use stepped stencil and via-in-pad rules to control voiding and tilt.

Tape & Reel parameters and placement orientation

Tape & Reel:

Verify pocket pitch, pocket depth, and leader/trailer length
Confirm reel size (e.g., 7″/13″) and quantity per reel for planning
Check ESD shielding and humidity indicators in the dry pack

Orientation:

Match pin-1 indicator (dot/notch) to PnP vision program
Confirm 0°/90° rotation expectations between vendor drawing and feeder
Run a first-article with X-ray/optical inspection for VSON/USON

ESD & handling:

Use ESD flooring, straps, and ionization near feeders
Avoid tweezers on package edges that define creepage distance

Download checklist / submit RFQ Open the packaging notes PDF

9) Pricing / Availability & Anti-Counterfeit

Small-batch procurement and anti-counterfeit checklist for photorelay/SSR. — Small-batch purchasing playbook: channel selection, incoming tests, lifecycle watch, and substitution readiness.

Module A — Relative pricing bands (spec-driven)

Use the following relative tiers to estimate cost pressure. Actual quotes vary by package, channel count, and lifecycle.

Spec dimension	Typical range	Relative price tier	Cost drivers / notes
V_LOAD rating	~30–600 V	Higher V → higher tier	Thicker die / stacks, tighter test; creepage-friendly packages cost more
I_LEAK (off leakage)	nA → low µA	Lower leakage → higher tier	Process selection, screening time, temp characterization add cost
R_ON (on resistance)	tens → sub-hundreds mΩ (family-dependent)	Lower R_ON → higher tier	Larger die / parallel structures; heat budget demands better packages
Speed (t_ON/t_OFF)	ms → sub-ms	Faster → higher tier	Higher LED drive / specialized drivers; sorting for symmetry
Channels / package	1 / 2 / 4 in SOP/SSOP/VSON	More channels & compact → higher tier	Density and yield; VSON/USON command premiums; MSL handling adds overhead

Rule of thumb: prioritize by constraint (leakage / R_ON / voltage / speed). For most DC/analog switching, leakage & C_OFF dominate cost more than absolute speed.

Module B — Small-batch sourcing & substitution

Price/lead time levers

Same family, different channels: dual/quad often higher unit price but lower cost per channel
Package swap: VSON/USON ↑ price & MSL; SOP/SSOP cheaper & easier to rework
Spec relaxation: slightly higher I_LEAK or R_ON can drop a tier with minimal system impact

“A not available → try B/C” play

Match V_LOAD, I_CONT, I_SURGE first; then I_LEAK / C_OFF / speed
Ensure AC capability (back-to-back) if needed; DC-only parts won’t block both polarities
Keep at least two pin-compatible alternates per footprint and voltage class

Lead time hygiene

Check lifecycle (Active/NRND/EOL) before BOM lock
Split by distributor to hedge allocation; confirm date codes and MSL on receipt
Plan a small PVT or pilot run to qualify alternates

Module C — Anti-counterfeit checklist

Channel first: prefer authorized distributors / franchised partners; keep proof of origin
Markings: verify pin-1 dot/notch style, font weight/spacing, and logo; compare with vendor marking guides
Date/lot code: check format vs. vendor convention; beware sanded lids or over-inked tops
Package cues: flash lines, mold vents, lead finish color, coplanarity — outliers are red flags
Incoming sample test: measure I_LEAK, R_ON, and timing on a few units across temperature
Electrical sanity: confirm AC versions really use back-to-back MOSFETs (bidirectional blocking)
Labels & bags: dry-pack label (MSL), HIC card, ESD symbols; mismatch suggests repack
Paper trail: retain invoices/COO/trace data; log reel IDs to batches for later correlation

Download checklist & RFQ Open selection checklist (PDF)

10) FAQs

Photorelay vs Optocoupler — what’s the difference?

An optocoupler transfers signals (LED→photodiode/transistor) but doesn’t switch load power. A photorelay is an isolated switch (LED input, MOSFET output) that carries load current. Use optocouplers for level shifting or feedback; use photorelays to open/close circuits with low leakage and no contact bounce. See Definition.

When to pick triac SSR vs MOSFET-output SSR?

Triac SSRs suit simple AC power control (heaters, lamps), often with zero-cross drive; expect mains EMI and dv/dt care. MOSFET SSRs (photorelays) excel in DC/analog precision: low leakage, low C_OFF, clean switching, AC possible via back-to-back MOSFETs. See Comparison and Applications.

In analog measurements, what do I_LEAK and C_OFF affect?

Off-state leakage biases high-impedance nodes and introduces measurement error. Off-capacitance limits bandwidth, slows settling, and increases crosstalk in MUX trees. Choose nA-class leakage and low C_OFF, route with guarding/shields, and validate across temperature. See Selection and Applications.

How to estimate on-loss and temperature rise?

Use P ≈ I²·R_ON, then ΔT ≈ P·θ_JA, and T_j ≈ T_amb + ΔT. Iterate because R_ON rises with T. Spread heat via copper/vias, and confirm surge/inrush. Try the worksheet in Design Notes.

dv/dt false turn-on — causes and cures?

Fast edges couple through output capacitance and internal paths, momentarily charging gates. Mitigate with RC snubbers (tuned for damping), tight loops, MOV/TVS for surges, and routing away from high-impedance nodes. Validate on the real load. See Design Notes.

Why back-to-back MOSFETs for AC loads?

A single MOSFET’s body diode conducts one polarity. Two MOSFETs in series, source-to-source (or drain-to-drain), block and conduct in both directions, enabling true AC switching and off-state blocking. See Definition and Design Notes.

How to choose LED drive current? Risks if too low/high?

Pick I_F from datasheet timing vs. current, then size series R with supply tolerance and V_F spread. Too low: slow or incomplete turn-on. Too high: LED aging/heat and wasted power. Consider a small driver transistor for timing control. See Design Notes.

t_ON/t_OFF vs load R/C — what’s the link?

The relay’s intrinsic timing plus the load’s RC define edge rates and settling. Higher C (load or wiring) slows transitions and increases charge injection artifacts. Validate with the intended source/load; symmetry may vary with I_F and output capacitance. See Design Notes.

Key points for 2×MOPP in medical designs?

Use reinforced insulation or two independent means; meet creepage/clearance for your working voltage and pollution degree. Control patient leakage, document compliance (CB/UL/VDE), and validate isolation over life and environment. See Safety & Reliability and Applications.

Handling pin compatibility and package differences when substituting?

Verify pin mapping, polarity markers, and recommended footprints. Re-check C_OFF, R_ON, leakage vs temperature, θ_JA, and AC capability (back-to-back). Keep at least two drop-in alternates per footprint. See Brands & Cross-Reference.

Controlling crosstalk and C_OFF in multi-channel MUX?

Choose low-C_OFF devices, shorten traces, add guarding/shield nets, and manage return paths. Stagger switching or settle before sampling. Consider channel-to-channel isolation specs and linearity. See Applications and Selection.

Why is my SSR “always on” or not fully off?

Common causes: dv/dt false turn-on, leakage biasing a high-impedance node, wiring capacitance, or using a DC-only part in AC paths. Add snubbers/TVS, provide bleed paths, and confirm back-to-back MOSFETs for AC. See Design Notes.

EMI risks when choosing faster devices?

Faster edges raise spectral content and ringing; coupling across the barrier or on I/O can increase emissions/susceptibility. Dampen with RC snubbers, soft drive, and tight loops; verify against system EMC limits. See Design Notes.

How to implement 4-wire switching in ATE MUX?

Use separate photorelays for force+ and sense+ (and force−/sense−), keep sense paths high-impedance and short, minimize R series, and ensure simultaneous or sequenced control to avoid transient errors. Validate settling and linearity. See Applications.

How to mitigate EOL/NRND risk early?

Track lifecycle (PCNs, NRND notices), select at least two pin-compatible families per footprint, and qualify alternates during EVT/DVT. Keep parametric slack (leakage/R_ON/voltage) to widen options and source via authorized distributors. See Cross-Reference and Pricing.