Transimpedance Amplifier (TIA): Current-to-Voltage Converter, Design & IC Selection Guide

A transimpedance amplifier (TIA) converts an input current into a proportional voltage, typically using an inverting op-amp with a feedback resistor (R_f).

TIAs present a low-impedance input for current-output sensors such as photodiodes, preserving linear conversion and bandwidth.

V_out = − I_in × R_f

To design a TIA that actually works in hardware, you must understand why its input must look like a virtual ground and how R_f/C_f shape gain and bandwidth — this is what we do next.

Why do we need a transimpedance amplifier? The case for a low-impedance “virtual ground”

Current-output sensors (e.g., photodiodes) read with a simple resistor suffer from load-dependent gain and slowed response as the node voltage rises. A TIA presents a near virtual ground—a low input impedance—so the sensor current flows almost entirely through the feedback path and converts linearly to voltage across R_f.

• Nonlinearity with a shunt resistor: node voltage alters sensor bias (I–V curve shifts) → readings distort.
• Bandwidth loss: node R with junction/trace capacitance (C_j) forms an RC pole that slows response.
• Noise & susceptibility: a high-impedance node picks up interference; a virtual ground limits coupling.
• TIA effect: closed-loop gain (Aβ) forces the node toward 0 V → effective Z_in becomes very low; current is “forced” through R_f.
• Result: predictable transimpedance gain and a clean starting point to set bandwidth and stability with R_f/C_f.

Knowing the “why”, we now look at the exact circuit topology and how R_f/C_f make it stable and fast.

How does a TIA circuit work? Inverting op-amp with R_f/C_f and a virtual-ground node

In a canonical TIA, the sensor (a current source such as a photodiode) connects to the inverting input, while the non-inverting input is tied to ground or a bias reference V_ref. The feedback network (R_f in parallel with C_f) and high loop gain hold the node at a near-virtual ground, so sensor current flows through R_f and becomes a voltage at the output.

R_f sets the DC transimpedance (current-to-voltage gain), while C_f together with junction/trace capacitances places zeros/poles that shape bandwidth and stability.

Input capacitance raises noise gain and can erode phase margin; the feedback capacitor C_f introduces a compensating zero to control the slope and recover stability (typical targets: 45–60° phase margin).

Non-inverting TIAs exist only under specific biasing or with preceeding transconductance/current-mirror stages; they are uncommon for photodiode readout. We focus on the inverting TIA here (see FAQ for edge cases).

• The inverting node is high-impedance and sensitive: keep traces short, use guard ring/shielding, and minimize parasitics.
• Consider small series input protection + ESD devices, balancing protection with added capacitance.
• Reverse-biasing photodiodes reduces junction capacitance C_j for speed, but watch dark current/noise changes.

Once the topology is clear, you can size R_f/C_f for gain, bandwidth, and noise — which is where real design begins. Continue to Key parameters & calculations.

Key parameters & calculations: gain, bandwidth, noise, and dynamic range

How to select a TIA? Choose R_f so the output stays within headroom at I_in,max, then size C_f with the sensor/op-amp capacitances to meet bandwidth and stability. How to calculate gain/bandwidth/noise? Use the formulas below (copyable) to estimate transimpedance gain, −3 dB bandwidth, and output noise; verify with simulation and adjust for phase margin.

3.1 Gain (selecting R_f)

With the inverting topology, the DC transimpedance is set by R_f:

3.2 Bandwidth (R_f·C and GBP coupling)

First-order approximation using the total capacitance at the inverting node:

Practical sizing with stability in mind:

1. Estimate C_sum = C_j + C_in + C_stray.
2. For a target f_{−3dB,target}, get a first-cut capacitor: C_f0 ≈ 1/(2π·R_f·f_target) − C_sum.
3. Refine C_f via simulation/bench to achieve ~45–60° phase margin (op-amp GBP and noise gain matter).

3.3 Noise (resistor/shot/voltage/current noise)

Output-referred noise spectral density (V/√Hz), main contributors:

• Resistor (Johnson): e_Rf = √(4·k·T·R_f)
• Op-amp current noise into R_f: e_i = i_n · R_f
• Sensor shot noise: e_shot = √(2·q·I_pd) · R_f
• Op-amp voltage noise via noise gain: e_en = e_n · NG(f)

3.4 Dynamic range (limits & trade-offs)

• Upper limit (saturation): set by V_headroom and R_f.
• Lower limit (sensitivity): set by i_eq,RMS (noise-equivalent current).
• Dynamic range (linear): DR ≈ 20·log10( I_in,max / i_eq,RMS ).

Worked example (copy & adapt)

Select Rf:   Rf ≤ 2 V / 50 µA = 40 kΩ  → choose Rf = 20 kΩ (margin, bandwidth-friendly)
Cap sums:    C_sum = Cj(10 pF) + Cin(3 pF) + C_stray(7 pF) ≈ 20 pF
First-cut Cf: Cf0 ≈ 1/(2π·Rf·f) − C_sum
              = 1/(2π·20k·200k) − 20pF ≈ 39.8 pF − 20 pF ≈ 19.8 pF  (fine-tune in sim/bench)

Noise @300 K:
  e_Rf   = √(4 k T Rf) = √(1.656e−20 · 20k) ≈ 18.2 nV/√Hz
  e_i    = i_n · Rf    = 2 pA/√Hz · 20k = 40 nV/√Hz
  e_shot = √(2 q I)·Rf with I_pd = 10 µA → √(3.204e−24)·20k ≈ 35.8 nV/√Hz
  e_en   (via NG) ≈ small first-cut

PSD sum:   e_out,PSD ≈ √(18.2²+40²+35.8²) ≈ 56.7 nV/√Hz
ENBW:      ≈ (π/2)·200 kHz ≈ 314 kHz
Total RMS: e_out,RMS ≈ 56.7 nV/√Hz · √314k ≈ 31.8 µV_RMS
Input eq.: i_eq,RMS ≈ 31.8 µV / 20 kΩ ≈ 1.59 nA_RMS

DR ~ 20·log10(50 µA / 1.59 nA) ≈ 90 dB (first-order estimate).
    

With R_f/C_f sized on paper, topology choices can further improve performance — single-ended, differential, or variable-gain TIAs. Continue to Topology choices.

Topology choices: single-ended, differential, and variable-gain TIAs (plus a transconductance comparison)

What is a differential TIA? A TIA with matched feedback on two sensor legs (e.g., balanced photodiodes) that produces a differential output with strong common-mode rejection for optical receivers.

What’s the difference between transconductance and transimpedance? Transconductance amplifiers convert voltage→current (G_m=I_out/V_in), while transimpedance amplifiers convert current→voltage (Z_t=V_out/I_in).

4.1 Single-ended TIA (the common default)

• When it fits: one photodiode, moderate dynamic range, typical EMI, single-ended ADC/backend.
• Pros: simplest BOM and routing; lowest cost and power; easy to debug.
• Trade-offs: no inherent common-mode rejection; high-impedance node is layout-sensitive (short traces, guard ring, shielding).
• Design echo from §3: larger R_f raises gain but lowers bandwidth with the same C_sum.

4.2 Differential TIA (balanced sensors, high CMRR)

A differential transimpedance amplifier uses matched feedback networks (R_f//C_f) on two sensor currents (e.g., a photodiode pair), yielding a differential output that rejects common-mode noise—ideal for optical receivers and long routes to differential ADCs.

• Benefits: high CMRR, improved immunity to supply/ground coupling, robust for high-speed links.
• Costs: tighter component matching, more area/power, more complex biasing and tuning.
• Design tips: match R_f/C_f, keep symmetry, align the differential common-mode with the ADC reference.

4.3 Variable-gain TIA (VG-TIA with AGC)

A variable gain transimpedance amplifier extends dynamic range by switching R_f, varying a front-end G_m, or digitally programming gain—useful when return signals vary widely (e.g., automotive LiDAR pulses).

• Implementations: stepped R_f ladder; variable G_m pre-stage + fixed R_f; mixed-signal control with MCU/FPGA.
• Trade-offs: gain-switching transients and added noise; AGC attack/release timing affects waveform fidelity and ranging accuracy.
• Use when: dynamic range is extreme; ambient and target reflections change by orders of magnitude.

4.4 TIA vs. transconductance (G_m) — direction and use cases

4.5 Decision checklist — when to pick which

• Choose single-ended TIA if: one sensor, moderate dynamic range, typical EMI, single-ended ADC.
• Choose differential TIA if: balanced sensors or strong common-mode noise, high-speed/long routing, differential ADC or LA.
• Choose VG-TIA if: signals span orders of magnitude (e.g., LiDAR), AGC transients are tolerable, control logic is available.
• Automotive/robustness: consider AEC-Q100 grade, temperature range, ESD/EMC strategy, and supply noise budget.

Once topology is chosen, you must implement it on a PCB that stays stable and quiet — layout and power now matter.

Design implementation: stability, compensation, PCB layout, and power

How to reduce TIA noise? Limit bandwidth with C_f, choose low-noise parts (C0G/NP0 + film R_f), minimize input capacitance and leakage with careful layout, and feed a clean supply/reference.

How to ensure stability? Model the total input capacitance, shape the noise-gain slope with C_f, and target ~45–60° phase margin using simulation plus step-response validation.

5.1 Stability & compensation (R_f/C_f, noise gain, phase margin)

• Total capacitance: C_total = C_f + C_j (sensor) + C_in (op-amp) + C_stray; larger C_total increases noise gain and reduces phase margin.
• Role of C_f: introduces a zero to tame the high-frequency slope; too small → under-compensation (ringing), too large → over-compensation (slow).
• Target margin: 45–60° (50–65° for high-speed links). Verify in AC simulation and with a time-domain step test.
• Preferred parts: C0G/NP0 for C_f; metal/foil or precision thin-film for R_f (low excess noise, low tempco).

5.2 PCB layout & grounding (high-impedance node care)

The inverting node is a high-impedance, leakage-sensitive point—layout here dominates real-world noise and accuracy.

5.3 Power & reference (LDO, decoupling, V_ref)

• Low-noise LDO with good PSRR in the signal band; add π-filter/ferrite if supply is shared with digital loads.
• Local decoupling: 0.1 µF (HF) + 1 µF (MF) + 10 µF (LF) close to pins; smallest loop area back to ground.
• Reference (V_ref): buffer or RC-filter it; keep impedance low and noise small for single-supply TIAs.
• Automotive/EMC: consider CISPR 25 / ISO 11452; evaluate common-mode chokes/ESD clamps and re-tune C_f if C_sum changes.

5.4 ESD & input protection (capacitance trade-off)

Protection must be “just enough”: every part you add increases parasitic capacitance and can reduce bandwidth/stability.

• Prefer ultra-low-C TVS (≤0.5–1 pF class).
• Add a small series resistor for surge limiting/damping if needed.
• Provide a clean reverse-bias network for photodiodes with proper decoupling/bleed; re-calculate C_sum after any changes.

5.5 Test & debug (scope/FFT/noise)

• Step tests: LED pulse or generator; inspect rise/fall, overshoot, settling error to classify compensation.
• Noise: band-limit and FFT; record ENBW and convert to input-equivalent current (see §3 formulas).
• Probing: beware probe capacitance; prefer low-C active probes or a local buffer/follower.

5.6 Design checklist (copy & use)

• Stability: target phase margin __ °; C_f sweep range = [__ pF, __ pF]; ENBW = __ kHz; cap type = C0G/NP0.
• Layout: inverting-node trace length < __ mm; guard ring present; feedback loop length < __ mm; differential symmetry (if any) within __ %.
• Power: LDO model __; PSRR @ freq __ = __ dB; decoupling 0.1/1/10 µF placed within __ mm; V_ref noise __ µV_rms.
• ESD/Protection: TVS C ≤ __ pF; series R __ Ω; reverse-bias network verified; post-change C_sum re-measured.
• Reliability: temp range __ to __ °C; derating applied; AEC-Q100 level (if applicable).

With a robust design in hand, let’s map it to real systems where constraints are different — optical links, LiDAR, medical, and precision metrology.

Transimpedance amplifier applications & signal chains

Across applications, a TIA’s constraints are set by the sensor current range, target bandwidth, noise ceiling, EMI/ESD environment, and the downstream interface (comparator/limiting amp/ADC/DSP). The blocks below map Sensor → TIA → post-amp/ADC → processor with typical ranges and common pitfalls.

6.1 Optical communication (optical receiver)

PIN/APD photodiode → differential TIA → limiting/linear post-amp or CTLE → CDR/ADC → DSP/PHY. Differential routing and matched feedback help preserve eye-diagrams at high data rates.

• Typical ranges: I_PD µA–mA; C_j 0.1–2 pF (PIN); f_−3dB 10–>100 MHz; tight phase margin.
• Pitfalls: APD bias noise coupling; CMRR loss from mismatch; supply/ground bounce; V_ref drift affecting decision threshold.

6.2 Automotive LiDAR & cameras

Photodiode/SPAD array → VG-TIA (AGC) → AA/LPF → ADC/ToF ASIC → SoC/ECU. Wide dynamic range and harsh EMC demand robust compensation and clean power.

• Typical ranges: I_PD nA–µA (pulsed); f_−3dB 100 kHz–10 MHz; −40~125 °C; AEC-Q100.
• Pitfalls: gain-switching transients; saturation/recovery from strong reflections; common-mode/ground noise; ISO 26262 safety interfaces.

6.3 Medical devices (oximeter/PPG)

LED optics → photodiode → low-noise single-ended TIA → LPF/gain → ADC → algorithms (SpO₂/PPG). Leakage and ENBW dominate sensitivity.

• Typical ranges: I_PD pA–µA; f_−3dB 10 Hz–100 kHz; extremely low i_eq required.
• Pitfalls: moisture-induced leakage and drift; motion artifacts; probe contact changes; V_ref noise injection.

6.4 Precision metrology (ultra-low current)

Ion/photocurrent/electrochemistry → high-R_f TIA with guarding → programmable filter/gain → high-resolution ADC → MCU/PC. Materials and cleanliness dominate accuracy.

• Typical ranges: I_IN fA–µA; R_f 100 kΩ–10 MΩ+; f_−3dB 10 Hz–1 kHz; minimize drift/1/f.
• Pitfalls: dielectric absorption; surface contamination (pA leakage); shield/ground details; thermal drift.

Now that constraints are clear per application, we can shortlist real ICs from major vendors that meet those constraints — continue to IC selection guide.

IC selection guide: cross-brand TIAs & AFEs (with fit-tags)

Map your calculated R_f/C_f, bandwidth, and noise targets to orderable parts. Below is a cross-brand list of transimpedance amplifier IC and op-amps used as TIAs, plus integrated AFEs. We include popular searches like TI OPA857, OPA855, onsemi NOA3306, and Renesas R-Car AFE. (We do not claim “the best”—we label fit-for-purpose.)

1. By application/bandwidth: optical / LiDAR / medical / metrology.
2. By span: I_in,max, V_headroom → limit R_f (see §3).
3. By noise: i_eq / ENBW targets → low-noise class.
4. By topology/robustness: single-ended / differential / VG-TIA; AEC-Q, temp, package.
5. Verify on EVM: bandwidth, phase margin, recovery, drift.

Brand notes & fit guidance

• Texas Instruments — rich OPA HS amps and dedicated TIAs; strong EVM ecosystem. Fit: high-speed optical, LiDAR, lab eval.
• STMicroelectronics — low-noise/low-power op-amps (medical/wearables), plus HS families for mid-speed TIAs.
• NXP — imaging/ToF AFEs for cameras/automotive; check platform docs for TIA path specs and AEC-Q status.
• Renesas — optical/vision AFEs and automotive platforms（e.g., R-Car AFE）；system-level integration focus.
• onsemi — optical/ambient/camera AFEs（e.g., NOA3306）；pairs well with their imagers.
• Microchip — zero-drift & low-noise op-amps for low-freq/precision TIAs; HS families for general optical.
• Melexis — ToF sensor AFEs with TIA paths, tuned for automotive perception.

Specs in the table are datasheet-driven. Fill concrete numbers and links from the latest DS/EVM pages; do not infer TIA-BW from GBP.

If your BOM already includes a TIA or you need cross-brand alternates, here is how we support real procurement and risk control.

Procurement & alternates: lead-time comparison, pin-compatible replacements, lifecycle & compliance

We provide lead time comparison across authorized channels, lifecycle checks (Active / NRND / EOL with PCNs), pin-compatible replacement proposals (with electrical deltas), and compliance verification (RoHS/REACH and automotive AEC-Q100 where applicable). We source only through authorized and traceable supply.

What you receive (deliverables)

• Comparison table for each MPN: brand/part/package, lead time (weeks), authorized stock, lifecycle (Active/NRND/EOL + PCN date/link).
• Pin-compatibility grade (L0/L1/L2) with electrical deltas (GBP, en/in, Iq, temp, AEC-Q, ESD, R_θJA).
• Compliance notes: RoHS/REACH certificates and AEC-Q100 grade if applicable.
• Risk tags (Supply / Lifecycle / Compliance) and two recommendations (conservative vs. aggressive).

How we work

1. Inputs: BOM (CSV/XLSX) with MPN, brand, qty, required date, alternates policy (strict/relaxed).
2. Normalization: de-alias parts, confirm package & temp grade.
3. Channel query: authorized only (factory & franchised distributors) for stock and lead time.
4. Risk modeling: Supply (availability trend), Lifecycle (Active→NRND→EOL timeline, PCNs), Compliance (RoHS/REACH/AEC-Q100 docs).
5. Outputs: downloadable PDF report + CSV detail with recommendations and test notes.

Before you submit a BOM, skim the common questions below—many are answered instantly. Continue to FAQ.

FAQs: transimpedance amplifiers (PAA-focused)

Downloadable resources (PDF)

Save, share, and deep-link these concise references. Each PDF is vector-based and aligns with the site’s visual system.

TIA Circuit Design Notes

What you’ll get: Copy-ready formulas, C_f selection flow, and a step-by-step worked example with layout & debug checklists.

Download PDF

Cross-brand TIA IC Selection Chart

What you’ll get: A cross-brand, spec-driven TIA/AFE shortlist with AEC-Q flags and datasheet/EVM links, ready for procurement.

Download PDF

Application Signal Chains

What you’ll get: Three application-grade signal chains with typical ranges and pitfalls to map your TIA to real systems.

Download PDF

Notes: parameters reflect latest datasheets where cited; app diagrams are self-drawn based on vendor application notes. For procurement and alternates, see §8.