Voltage Supervisor & Reset ICs: Brownout Immunity

Why External Voltage Supervisors Matter

Brownouts and noisy ramps often cause nuisance resets or release the MCU too early. An external supervisor adds precise thresholds, hysteresis, and reset delay—so rails settle before firmware runs. Small-batch friendly? Send your BOM and get a 48-hour short-list with pin-to-pin options.

Minimal blue cover: supply rails feed a window supervisor; outputs reset pulse and power-good check.

Submit your BOM (48h)

Problems We Solve

Real boards brown out, ripple, and boot inconsistently. These six issues cause nuisance resets, early releases, and fragile bring-up. Each card ends with a fast route to the spec rules you can apply today.

Threshold too tight/loose → nuisance or missed brownouts

If V_TH sits inside the ripple band, resets chatter; if too loose, true brownouts pass.

Size hysteresis to ≥(ripple+noise)×1.2 and consider a window supervisor when both UV and OV matter.

See fast rules →

No hysteresis → reset chatter

At the boundary the rail crosses back and forth, toggling RST and corrupting start-up.

Use ΔV_HYS ≥ ripple band, add RC deglitch or hold-off delay to let rails and clocks settle.

See fast rules →

Reset delay too short → rails/clock not valid

Early MCU release causes random faults, especially on cold start and heavy loads.

Choose t_DELAY ≥ slowest-rail settling + 10–20% margin; then re-verify with watchdog enabled.

See fast rules →

Watchdog cadence mismatch (WDI) → false timeouts

OS tick, sleep modes, and WDI window drift apart; “healthy” firmware times out.

Align cadence to a single clock source; gate/disable watchdog during bring-up and deep-sleep.

See fast rules →

PG and RESET logic conflict (OR/AND wiring)

Mixed polarities and levels make PG OR chains unreliable—either early release or no release.

Prefer open-drain with a known pull-up level; verify polarity and leakage on every contributor.

See fast rules →

Multi-rail sequencing errors → brownout cascade

Wrong order or insufficient spacing triggers downstream BOD and a reset storm.

Use window + delay to constrain both voltage and timing; split into multi-channel supervision if needed.

See fast rules →

Architectures & Types

Single-threshold

Simple, low power for clean rails. Needs correct hysteresis and reset delay to avoid boundary chatter.

Window (UV + OV)

Enforces both lower and upper bounds to resist ripple/over-voltage; ideal for noisy or sensitive rails.

Multi-rail / Programmable

Multiple channels, programmable thresholds/delays for complex sequencing with fewer external parts.

Watchdog-enabled

WDI/WDO guards firmware hangs; align cadence with OS tick and gate it during bring-up or deep sleep.

Outputs & Polarity

Open-drain eases OR-wiring; push-pull gives strong drive. Match polarity and pull-up level to MCU limits.

Understand the key specs that prevent chatter and early-release resets → jump to #features. Need a 48-hour shortlist? Submit your BOM.

Key Specs & Fast Rules

V_TH Accuracy Choose accuracy by rail criticality. Tighter parts reduce early/late release risk.

Hysteresis ΔV_HYS Set ≥ 1.2–1.5× (ripple + fast noise) to prevent reset chatter.

Delay t_DELAY / t_RST Hold reset until rails & clock are valid; keep reset width ≥ 1.2–1.5× MCU min.

Output Type & Polarity Open-Drain eases OR-wiring; Push-Pull gives strong drive. Match active-L/H & levels.

Threshold Tempco Budget device + divider drift; keep limits safe across worst-case temperature.

Operating Temp / AEC-Q100 Pick grade for ambient profile (G0/G1/G2/G3). Verify derating at extremes.

ESD (HBM/CDM) ESD rating ≠ system protection—add TVS/filters where required.

Fast Rules You Can Apply Today

Threshold & Hysteresis

ΔV_HYS ≥ 1.2–1.5 × (ripple + noise); use upper bound for noisy rails.
Target V_TH,lo ≈ 10–15% below minimum steady voltage; V_TH,hi ≈ 5–8% above.
Need UV & OV control? Choose a window supervisor.

Delay & Reset Width

t_DELAY ≥ max( slowest rail settle, PLL lock ) × 1.1–1.2.
t_RST ≥ 1.2–1.5 × MCU minimum reset pulse width.

Outputs, Polarity & Levels

Prefer Open-Drain for multi-source OR; unify the pull-up rail across contributors.
Keep pull-up ≤ MCU absolute max (including transients); use level shifting if domains differ.
Push-Pull is cleaner but less flexible across domains.

Temperature & Reliability

Sum device tempco + divider drift + wiring drop; re-validate margins at hot/cold.
Match AEC-Q100 grade to environment; ESD rating augments—not replaces—system protection.

Open-drain with pull-up for OR-wiring vs push-pull direct drive; check levels and polarity. — OD simplifies OR-wiring; PP provides strong drive—match levels.

Three-Step Quick Pick

Set thresholds & hysteresis: enter ripple/noise and allowed false-reset rate → get ΔV_HYS range; pick single or window.
Choose delays: use slowest rail settle/PLL lock/storage init → size t_DELAY & t_RST.
Select outputs & polarity: match MCU RST/PG logic and voltage domains (OD/PP, Active-L/H).

Shortlist concrete parts → jump to the Selection Matrix.

Selection Matrix — 7 Brands

We can assemble a cross-brand pin-to-pin matrix in 48h. Submit your BOM for exact parts and the smallest rework path.

Brand	Channels	V_TH	Window	t_DELAY / t_RST	Reset Type (OD/PP, Polarity)	Watchdog	PG	Temp Grade	AEC-Q100	Package	Notes (Pin-to-Pin / Rework)
TI	1 / 2 / Multi	Steps / Fixed	UV / UV+OV	Programmable ranges	OD / PP, Active-L/H	Optional	Yes/No	-40~125/150℃	G0–G3	SOT-23 / DFN	Pin-to-pin options; verify pull-up rail vs MCU max.
ST	1 / 2	Common rails covered	UV / UV+OV	ms-level options	OD / PP, Active-L/H	Variants	Yes/No	-40~125℃	G1–G3	SOT-23 / DFN	Small packages; check polarity match.
NXP	Multi-rail focus	Fixed / Programmable	Window options	Wide timing spans	OD / PP, Active-L/H	Yes	Yes	-40~125/150℃	G0–G2	TSSOP / QFN	MCU-centric; check domain levels.
Renesas	1 / Multi	High accuracy options	UV / Window	Programmable / fixed	OD / PP, Active-L/H	Yes/No	Yes/No	-40~125℃+	G1–G3	SOT / DFN / QFN	Precision thresholds; verify tempco budget.
onsemi	1 / 2	Common fixed steps	UV / Window	ms ranges	OD / PP, Active-L/H	Variants	Yes/No	-40~125℃	G2–G3	SOT-23 / TSOP	Classic single/dual rail; confirm polarity.
Microchip	1 / 2	Low-power steps	UV / Window	Fixed / selectable	OD / PP, Active-L/H	Yes/No	Yes/No	-40~125℃	G2–G3	SOT-23 / SOT-143	Compact; check t_DELAY differences vs original.
(Slot 7)	TBD	TBD	TBD	TBD	TBD	TBD	TBD	TBD	TBD	TBD	Use this slot for ADI/Maxim / ROHM / ABLIC per needs.

Need pin-to-pin options fast? Get pin-compatible options.

Design & Routing

Wire supervisors to be level-safe, chatter-proof, and sequencing-aware. Use pull-ups that meet sink and rise-time limits, match logic polarity, and avoid hard-ORing push-pull outputs across domains.

Pull-up value & pull-up rail

Typical 3.3–5 V logic: 4.7–47 kΩ. Heavier fan-in or faster edges → 4.7–10 kΩ; low-power single sink → 22–47 kΩ.

Check sink: I_sink ≥ V_PU/R_PU and VOL spec. Check rise: t_r ≈ R_PU·C_load ≤ 0.1× timing margin.

Level compatibility to MCU

Pull up to a rail ≤ MCU absolute max and within its VIH/VIL range. Crossing domains? Use level shifting or move the pull-up to the MCU domain.

Open-Drain vs Push-Pull mixing

Open-Drain (OD) is safe for multi-source OR with a shared pull-up. Do not tie two push-pull drivers together—use diodes/resistors or a logic gate.

Cross-domain level shifting

Prefer OD+pull-up to the target domain. For push-pull across domains, insert a dedicated level shifter or buffer with defined thresholds.

Work with LDO/DC-DC EN pins

Align polarity and level first. EN pins may include their own threshold/hysteresis—avoid double-hysteresis that shifts release earlier/later than intended.

Open-drain with pull-up for OR-wiring vs push-pull direct drive; check levels, polarity and EN wiring. — OD eases OR-wiring and cross-domain pulls; PP provides strong drive—match levels and polarity.

Don’t

Pull up RST/PG to a rail above the MCU absolute max.

Use the lowest common safe domain or add a level shifter.

Don’t

Hard-OR two push-pull outputs.

Use OD+pull-up, diode-OR, or a logic gate for combining signals.

Don’t

Ignore R_PU×C_load rise-time on long nets or many sinks.

Size R_PU so t_r ≤ 10% of your timing margin.

Don’t

Feed inverted PG directly to EN/MCU without checking polarity.

Normalize polarity and consider EN’s own threshold/hysteresis.

Need a level-safety check? Revisit the key specs, then shortlist parts in the matrix.

Timing & Validation

Validate with a repeatable scope script: stress cold/hot starts, slow ramps, dips, and under-voltage depth. Trigger on reset edges and threshold crossings, then judge against clear pass/fail limits.

Test matrix

Cold start (lowest temp, heaviest load)
Hot start (highest temp, typical load)
Slow ramp (soft source / high capacitance)
Drop/bounce (battery insert/remove, dV/dt sweep)
Under-voltage depth sweep below V_TH,lo

Scope setup

Channels: Rail / RST / PG / EN / WDI (≥3–4 active)
Bandwidth limit ~20 MHz to tame HF noise
Sample rate ≥ 10× highest event bandwidth
Record length ≥ t_DELAY + t_RST + safety window
Trigger: RST edge; secondary on V crossing V_TH

Log each run

Ambient, source, load, probes, grounding
Measured V_TH,hi/lo, ΔV_HYS, t_DELAY, t_RST

Brownout timing: rail dips below threshold, reset asserts, delay holds, then release after recovery. — Trigger on reset; verify release only after the stable window.

Metric	Pass	Fail
Threshold crossings	Single clean crossing per event	Multiple back-and-forth chatter
ΔV_HYS	≥ 1.2×(ripple+noise) target	< target; chatter observed
t_DELAY	≥ max(rail settle, PLL lock)×1.1–1.2	Early release vs slowest rail/PLL
t_RST width	≥ 1.2–1.5× MCU min reset pulse	Below MCU min or marginal boot
Chatter count (start/dip)	0 events within the window	≥1 event within the window
PG→EN timing	Within required enable window	Too early/late for downstream
Watchdog (bring-up)	Disabled/gated; no false timeouts	False timeouts during bring-up

Download the full timing script and bring-up checklist → go to Resources.

Automotive / Industrial Notes

AEC-Q100 grade matches ambient range—not the whole system robustness. Plan for threshold and delay drift across temperature and aging, and run pre-compliance checks for conducted/radiated noise and ESD before design freeze.

Grade	Typical V_TH Drift	Typical t_DELAY Drift	Notes
G0 (-40~150 °C)	Tightest bin; budget device+divider tempco over full span	Slight increase at hot; verify worst-case PLL/rail settle	Test at -40/25/150 °C; add ΔV_HYS margin for cold crank
G1 (-40~125 °C)	Moderate drift; divider tempco dominates if high values	Delay stretch at hot; confirm reset width remains ≥ spec	Validate EN thresholds vs PG at hot soak
G2 (-40~105 °C)	Looser drift; add extra hysteresis in noisy domains	Check early-release on slow supplies	Thermal profiling still required for corners
G3 (0~85 °C)	Largest drift budget; design for room-temp first, verify at 0/85 °C	Delay vary with RC tolerances; guard with margin	Industrial use only; automotive under-hood not suitable

Conducted / Radiated immunity

Add RC/filters near sense pins and keep ground return short to avoid false thresholds.

ESD strategy

HBM/CDM is a device rating only—use TVS, common-mode chokes, and routing discipline for system ESD.

Harness / common ground

Place pull-ups close to receivers; avoid long OR chains and level conflicts between domains.

Need a Grade 0 option? Ask us for verified parts.

Pin-Compatible & Cross-Brand

Prioritize physical compatibility first, then electrical behavior. Follow this order to minimize rework and validation time.

Package & pinout — exact footprint/pin order first.
Polarity — match RESET/PG active level; avoid logic flips.
V_TH / Window proximity — keep thresholds or UV/OV window close.
t_DELAY / t_RST — align release and reset width.
Watchdog / PG features — keep behavior consistent when enabled.

Pull-up voltage

Different pull-up rails can exceed MCU absolute max or miss VIH—normalize levels or shift.

Polarity change

Active-L/H mismatch requires inversion and software/bring-up retest.

Delay mismatch

Different t_DELAY shifts release under cold/hot/slow-ramp corners—re-measure timing.

Tempco drift

Combined tempco of device and divider moves thresholds—watch for edge resets.

We can propose minimal-rework swaps with a risk note — Submit your BOM.

FAQs

Concise answers with actionable rules. Open each item to see guidance and links to the relevant section.

Window vs single-threshold — when should I choose each?

Pick single-threshold on clean rails with predictable ramps; add adequate hysteresis and delay. Choose a window supervisor when ripple is high, both UV and OV matter, or multi-rail interactions risk over-voltage release. Window control reduces nuisance resets and early MCU release. Learn more → #architectures, #features.

How much hysteresis is enough relative to ripple and noise?

Size ΔV_HYS to at least 1.2–1.5× the sum of ripple and fast noise on the monitored node. Use the upper bound for switch-mode rails or long traces. If chatter persists, add deglitch/RC and reassess the delay. Window supervisors further suppress false toggles. Learn more → #features.

Reset delay vs reset width — how do they interact?

Reset delay holds release until rails and clocks are truly valid. Reset width guarantees the minimum pulse for the MCU. Make t_DELAY ≥ max(rail-settle, PLL-lock)×1.1–1.2, and t_RST ≥ 1.2–1.5× the MCU minimum. Verify both under cold/hot and slow ramp. Learn more → #features, #timing.

Is it safe to pull an open-drain output up to a higher voltage rail?

Only if the higher rail does not exceed the MCU input absolute maximum and meets VIH/VIL. Normalize levels by pulling up to the MCU domain or use a level shifter. Check sink current and rise time with R_PU×C_load. Mixed domains need extra care. Learn more → #design.

Can I mix open-drain and push-pull sources on the same net?

Do not hard-wire two push-pull drivers together. Use open-drain with a common pull-up for wired-OR, or combine with diodes/resistors or a logic gate. Align polarity and ensure the pull-up rail is safe for every participant. Validate leakage and contention. Learn more → #design.

What are the hidden risks of PG OR (wired-OR / diode-OR) networks?

Mixed polarities, unequal pull-ups, and leakage can create early or never-release conditions. Verify level compatibility, total pull-up strength, and diode drops. Prefer open-drain contributors with a shared rail and defined polarity; avoid mixing push-pull without logic. Learn more → #design.

How do I align watchdog WDI cadence with OS tick and sleep modes?

Derive the WDI service from a single stable clock source and pause or window-extend during bring-up and deep-sleep. Validate across DVFS and low-power states to avoid false timeouts. If cadence varies widely, use a window watchdog or gate WDI in firmware. Learn more → #features, #timing.

Cold/hot start and slow ramp — what should my scope triggers be?

Trigger on the reset edge as primary, with a secondary level trigger at the threshold crossing. Use ≥10× bandwidth sampling and record length covering t_DELAY+t_RST+margin. Compare averaged and raw captures; judge with raw data. Learn more → #timing.

How do temperature drift and aging move thresholds and delay?

Combine device tempco, divider drift, and wiring drop. Thresholds typically shift at hot and cold; RC-based delays elongate at hot. Budget margins so ΔV_HYS and t_DELAY remain valid at corners, then verify at -40/25/125 °C (or 150 °C for Grade 0). Learn more → #reliability.

AEC-Q100 grades — what do G0/G1/G2/G3 practically change?

Grades define qualified temperature ranges and stress coverage. G0 supports -40 to 150 °C; G1 to 125 °C; G2 to 105 °C; G3 to 85 °C. Grade is a device claim, not a system guarantee—run EMC, ESD, and corner timing validations regardless. Learn more → #reliability.

How do I coordinate supervisor outputs with LDO/DC-DC EN pins?

Normalize polarity first, then ensure EN thresholds and hysteresis align with PG/RST timing. Avoid double hysteresis that shifts release earlier or later. For cross-domain control, prefer open-drain to the destination rail or add a proper level shifter. Learn more → #design.

MCU BOD vs external supervisor — should I use both?

Built-in brownout detect is convenient but often lacks programmable delay and robust hysteresis. An external supervisor enforces rail-first, firmware-second behavior and coordinates multi-rail PG. Use both when safety or noisy environments demand redundancy. Verify polarity and timing interactions. Learn more → #features, #design.

Multi-rail sequencing — how do I avoid brownout cascades?

Constrain both voltage and time: window thresholds per rail and appropriate inter-rail delays. OR PG signals carefully—prefer open-drain contributors and consistent pull-ups. Validate order under slow ramp and fast dips with clear pass/fail metrics. Learn more → #architectures, #timing.

Pin-to-pin across brands — what deviations are acceptable?

Prioritize package and pinout, then polarity. Keep V_TH/window close, align t_DELAY/t_RST, and match watchdog/PG behavior. Document differences: pull-up rail, active level, delay skew, tempco. Re-run timing at corners before release. Learn more → #alternatives, #selection.

Still unsure? Submit your BOM for a 48h matrix.

Resources & RFQ

Download ready-to-run worksheets and scope scripts to size thresholds, delays, and validate timing. Then send your BOM for a cross-brand shortlist in 48 hours.