eFuse Power Switch IC: Inrush, OVP, Reverse-Block & Alternatives

eFuse (Electronic Fuse) — At a Glance

An eFuse is a resettable power-switch IC that protects rails by electronically shutting off a built-in MOSFET.

Detection — monitors current/voltage against set thresholds.
Interruption — controller shuts the MOSFET to stop the fault.
Reset — auto-retry or host re-enable after the fault clears.

OVP clamp to handle voltage spikes.
Reverse-current blocking to stop backfeed.
Inrush suppression via adjustable dv/dt or current limit.

Hot-swap boards · Automotive 12/24 V · Storage/SSD rails · Consumer devices

eFuse at a glance: MOSFET shut-off, OVP clamp, reverse-current blocking, inrush control

What is an eFuse (Power-Switch IC)

An eFuse is a resettable power-switch IC that protects power rails. Unlike traditional fuses that melt, an eFuse senses faults and electronically shuts off an integrated MOSFET.

What you get — and when you need it

ILIM (current limit) — When: you must control inrush or short overcurrent bursts.
OVP (over-voltage protect / clamp) — When: supply has spikes, unstable adapters, or backplane transients.
UVLO (under-voltage lockout) — When: avoid brown-out chatter and undefined behavior at low input.
dv/dt soft-start (slew rate) — When: large output capacitors or sensitive loads require smooth ramp-up.
Reverse-current blocking — When: prevent backfeed during power-muxing, battery reversal, or shutdown.
PG/FAULT pins & I²C programmability — When: you need status, telemetry, or adjustable thresholds.

Not ideal for: very high-power hot-swap domains that require large SOA — use a hot-swap controller with external MOSFETs instead.

Mini glossary (tap to expand)

ILIM: current-limit setpoint; OVP: spike clamp or fast cut-off; UVLO: disable below safe input; dv/dt: controlled start-up ramp; PG: power-good indicator; FAULT: fault status pin; I²C: digital interface for configuration.

Need small-lot parts (1–1000 pcs)? See buying scenarios →

eFuse internal block diagram: sense & control, driver, integrated MOSFET to the load

How an eFuse Works: Detection → Interruption → Reset

The eFuse principle is a three-stage fault response: detect the anomaly, stop it by shutting the MOSFET, then recover safely.

Detection — sense current/voltage, apply blanking/deglitch filtering.
Interruption — limit or quickly shut off; controller pulls the MOSFET gate low.
Reset — auto-retry after a cool-down or latch-off until the host clears the fault.

Speed vs False Triggers — tuning thresholds & filtering

t_blank (blanking/deglitch) too short → ultra-fast, but noise & inrush spikes may trip; too long → real faults may pass energy.
Thresholds (ILIM/OVP) tighter → stronger protection yet less tolerance to transients or load steps.
Practical tip: estimate worst-case inrush, then coordinate with dv/dt soft-start to lower nuisance trips.

Reset modes: Auto-retry vs Latch

Auto-retry — periodic re-enable after cool-down (t_retry); pros: self-healing; cons: potential flicker/thermal cycling.
Latch-off — stays off until host clears FAULT; pros: predictable & safe; cons: requires user/MCU intervention.
Rule of thumb: consumer/remote gear → auto-retry (limit duty cycle); automotive/critical loads → latch-off with PG/FAULT reporting.

Engineer’s checklist

Estimate worst-case inrush → refine with dv/dt or current-limit mode.
Set ILIM/OVP/UVLO with 10–20% margin; validate with load steps and line transients.
Start t_blank ≈ 1–2× noise pulse width; shrink until false trips appear, then back off.
If auto-retry, cap the retry duty cycle to avoid heating; if latch-off, design a clear-fault path.
Wire PG/FAULT to MCU/logger; record events for field diagnostics (see protection functions).

eFuse fault timing (A-variant): short t_blank and fast response from overcurrent to limit/shutoff; VIN, VOUT, IOUT, GATE, PG, FAULT annotated — A-variant: **short blanking + fast response** — minimal delay to limit/shutoff, PG drops and FAULT asserts promptly.

eFuse reset modes: auto-retry with cooldown (t_retry) versus latch-off requiring host clear — Reset behavior: **auto-retry** (periodic attempts) vs **latch-off** (host-cleared).

eFuse vs MOSFET / Load Switch / Hot-Swap / PTC / HSD — Decision Guide

Pick the switch by protection needs and power level—integration vs external-FET capability.

Decision tree: choose eFuse, load switch, hot-swap + external MOSFET, PTC/fuse, or HSD based on protection features and power level — Start with required protections (ILIM/OVP/Reverse-block/dv/dt), then check power/thermal headroom.

Rule #1 — Integration First

Need precise current limit, OVP, reverse-current blocking, or controlled dv/dt? Choose an eFuse for built-in protection & diagnostics (PG/FAULT).

Rule #2 — Power Boundary

For very high current or hot-swap SOA, use a Hot-Swap controller + external MOSFET. eFuse fits low-to-mid power rails.

Quick matrix — ✔︎ strong · ○ limited · — none
Aspect	eFuse	Load Switch	Hot-Swap + FET	PTC / Fuse	MOSFET (discrete)	HSD (high-side driver)
Typical V/I range	Low–Mid V, up to Mid I*	Low V / Low–Mid I	Mid–High V / High I (SOA via FET)	Broad V / I (passive)	Any (depends on FET)	Automotive 12/24 V loads
Integrated protections (ILIM/OVP/dv/dt/Reverse-block/PG/FAULT)	✔︎ (rich)	○ (basic soft-start)	○–✔︎ (controller-dependent)	— (no electronics)	— (needs extra ICs)	○ (diagnostics for loads)
Fault response speed (short/OVP)	✔︎ (fast electronic)	○ (limited)	✔︎ (with tuned controller)	— (slow trip/thermal)	— (depends on external logic)	○ (not for rail protection)
Power / thermal headroom	○ (package-limited)	○ (limited by Rds(on))	✔︎ (scales with FET SOA)	○ (adds series R/heat)	✔︎ (choose proper FET)	○ (for loads, not rails)
Design complexity / tuning effort	Low (integrated settings)	Low (simple on/off)	High (FET + SOA + tuning)	Low (passive-only)	Medium (needs external control)	Medium (load-dependent)
Diagnostics / programmability	✔︎ (PG/FAULT, I²C options)	— / ○ (few signals)	○–✔︎ (vendor-specific)	— (none)	— (external IC needed)	○ (diagnose loads)
Cost / BOM impact (relative)	Medium (saves externals)	Low (lowest)	Medium–High (multi-device)	Low (but weaker performance)	Low (FET is cheap)	Medium (feature-specific)
Recoverability (resettable)	✔︎ (auto-retry/latch)	○ (limited)	✔︎ (controller-set)	— (one-shot/slow reset)	— (depends on logic)	○ (driver restart)
Typical use cases	SSD/FPGA rails, USB-C ports, 12/24 V subsystems	Simple load on/off, low inrush needs	Server backplanes, telecom cards, big batteries	Basic fault containment, low-cost appliances	General switching (needs protection ICs)	Lighting, body ECUs, solenoids (PWM)

* eFuse continuous current is package/thermal-limited; verify Rds(on)×I²R and layout. Use dv/dt to tame inrush.

SSD 5 V Rail (mid-current)

eFuse wins: adjustable dv/dt limits inrush, precise ILIM protects connectors, reverse-block avoids backfeed, and PG/FAULT eases diagnostics.

Server 12 V Backplane (high current hot-swap)

Hot-Swap + external MOSFET: controller tunes SOA and dV/dt for large capacitive loads; scalable with parallel FETs for thermal margin.

Common pitfalls

Treating HSD as a rail protector — it drives loads, it doesn’t replace eFuse protections.
Relying on PTC alone — slow/rough trip, poor for interfaces or storage rails.
Ignoring thermal — eFuse Rds(on) × I²R needs copper area/thermal vias; validate in your layout.

See small-lot cross-brand picks → Pin-to-pin notes & lead-time compare

Inrush & dv/dt — Control the Peak, Stabilize the Rail

Slower dv/dt means smaller inrush. An eFuse caps I_peak with a controlled ramp or current limit.

Core formula: I_peak = C · dV/dt or with ramp time I_peak = C · V_out / t_r

Ex.1 C = 200 µF, dV/dt = 1 V/ms → I_peak = 0.2 A
Ex.2 C = 100 µF, V_out = 5 V, t_r = 2 ms → I_peak = 0.25 A
Ex.3 C = 470 µF, V_out = 12 V, t_r = 10 ms → I_peak ≈ 0.56 A

Tip: MLCC effective capacitance drops under DC bias/temperature—use 60–80% of nameplate for estimates.

Open Inrush Calculator Input C, V_out, and ramp time or dv/dt to get I_peak.

Measure correctly: the window changes the “peak” you see

Sampling/averaging windows alter the reported peak. Declare probe bandwidth and window when validating inrush after dv/dt or current-limit tuning.

Current-limit behaviors — thermal & recoverability

Aspect	Constant current	Foldback	Hiccup
Thermal stress	Highest (P ≈ V_drop·I_lim)	Lower (I reduces with V_out)	Lowest (low duty cycle)
Recoverability	Stable if cooled; risk of thermal shutdown	Moderate; may lengthen start-up under heavy load	Automatic; periodic reattempts
Impact on load	Smooth; best for digital/IO rails	Slower rise; OK for tolerant loads	May flicker; check system tolerance
Typical use	SSD/FPGA, USB-C ports	Bigger capacitive rails	Harsh shorts / thermal limits
Notes	Validate heat at worst case	May need longer t_r	Limit retry duty cycle

Engineer’s checklist

Estimate C_eff (electrolytic + MLCC; use 0.6–0.8× nameplate for MLCC).
Decide safe I_peak (≤ connector/PSU/wiring limits).
Compute t_r = C·V_out/I_peak or dv/dt = I_peak/C.
Select limit mode: constant for stability; foldback/hiccup when heat is critical.
Verify with stated measurement window; re-check at hot/cold/low VIN. See protection functions for OVP/reverse-block tuning.

Working at very high current? Check when to move to a hot-swap controller in the comparison section.

Inrush measurement window comparison: same waveform shows different peaks under 100 µs vs 1 ms windows — Same waveform, different sampled peak — declare probe bandwidth and averaging window.

dv/dt (or ramp time) vs inrush current I_peak for a given capacitance — Slower dv/dt (longer ramp) reduces I_peak for the same capacitance.

Protection Functions — OVP Clamp, Reverse-Current, Short-Circuit & Thermal

An eFuse combines configurable protections: reverse-current blocking, OVP clamp or shut-off, short-circuit handling (constant/foldback/hiccup), and thermal shutdown. This section gives practical decision points and a quick trigger & recovery table.

Reverse-Current Blocking

Where needed: power ORing/muxing, backfeed on shutdown, battery reversal, USB-C bidirectional ports.
Topologies: single-FET eFuse blocks source→load; back-to-back FETs block both directions (typical).
vs Ideal-Diode controller: ideal-diode excels at low-drop ORing; eFuse adds precise limit/OVP/telemetry.
Test tip: perform sink-current tests with the downstream node driven high; verify backfeed clamp during power-down.

OVP Clamp vs Fast Shut-off

Clamp: holds V_OUT ≈ V_clamp to ride through spikes; thermal cost P ≈ (V_IN−V_clamp)·I — check SOA/heat.
Shut-off: cuts the path quickly; minimal heat but may cause a momentary load drop/reset.
Pick it: sensitive loads → Clamp (use TVS to share energy); large/long surges → Shut-off.
Automotive: ISO 7637 & load-dump usually need TVS + eFuse co-design (see automotive).

OVP strategies: output clamp at Vclamp vs fast shut-off; thermal trade-offs and continuity — OVP options: hold with clamp vs cut off — choose continuity or minimal heat.

Short-Circuit Handling — Constant / Foldback / Hiccup

Constant current: smoothest for digital/UI rails; highest dissipation during faults.
Foldback: I_LIM decreases as V_OUT collapses; lowers heat but can slow heavy start-up.
Hiccup: periodic attempts with low duty cycle; lowest average heat yet may cause visible flicker.
Coordinate with dv/dt soft-start to reduce nuisance trips; avoid too-low I_LIM that prevents start-up.

Thermal Shutdown & Derating

Heat sources: R_DS(on)·I²R, clamp energy, and V_drop·I_LIM during limits/shorts.
Layout: watch R_θJA; use copper pour, thermal vias, and a well-tied exposed pad.
Strategy: for auto-retry, constrain duty-cycle; for critical/automotive loads, use latch-off + FAULT/PG reporting.

Trigger & Recovery quick reference — PG: power-good, FAULT: fault indicator
Condition	Trigger / Threshold	Action	PG	FAULT	Recovery	Notes
Overcurrent	I > I_LIM (blanked)	Limit or shut-off	Low	Assert	Auto-retry or latch-off	Tune dv/dt to reduce false trips
Short-circuit	Very low V_OUT + high I	Const./foldback/hiccup	Low	Assert	Auto-retry or latch-off	Check thermal headroom
Reverse current	I_rev detected / V_OUT>V_IN	Block / shut-off path	Low (if path opens)	Optional	Auto when condition clears	Prefer back-to-back FETs
OVP (spike)	V_IN > V_OVP	Clamp or shut-off fast	Low (if out of spec)	Assert	Auto when VIN normal; latch if set	Use TVS for ISO pulses
UVLO	V_IN < V_UVLO	Disable output	Low	Optional	Auto when VIN recovers	Prevents brown-out chatter
Thermal shutdown	T_J > T_SD (typ.)	Shut-off; cool down	Low	Assert	Auto when cool or latch	Limit retry duty-cycle

Engineer’s checklist

From dv/dt, set target I_peak and ramp time; avoid too-low I_LIM that blocks start-up.
Set ILIM/OVP/UVLO with 10–20% margin vs worst-case rails & load steps.
Need ORing/backfeed immunity? choose back-to-back FET eFuse.
Choosing Clamp? estimate P=(V_IN−V_clamp)·I & duration; pair with TVS.
For high-power rails, review the boundary in the comparison section (hot-swap + external FET).

Need parts with reverse-block & OVP? See small-lot picks →

Automotive 12/24 V — ISO 7637, Load Dump, Harness & Thermal

In vehicles, harness inductance and load switching create harsh transients. TVS absorbs energy while the eFuse limits/blocks (ILIM, OVP clamp/shut-off, reverse-current, reset behavior). Co-design is key.

Automotive co-design: Battery → TVS → eFuse → Bulk cap → DC/DC → Load; handling ISO 7637 pulses and load dump — Battery → **TVS** (energy clamp) → **eFuse** (limit/OVP/reverse-block) → Bulk cap → DC/DC → Load.

ISO 7637 / Load Dump — quick co-design guide (TVS + eFuse)
Event	Phenomenon	Typical cause	Primary protection	Notes
Pulse 1 (− spike)	Negative kick on supply	Inductive loads opening	TVS (bidirectional), eFuse UVLO	Route returns tightly; check MCU brownout
Pulse 2a (+ spike)	Fast positive spike	Alternator switching, relay bounce	TVS, eFuse OVP clamp	Clamp continuity vs shut-off choice
Pulse 2b (+ spike)	Positive spike, slower tail	Switched inductive source	TVS, eFuse clamp/shut-off	Energy may be non-trivial → thermal check
Pulse 3a/3b (fast)	Fast ± transients (EMI-like)	Switching, ESD-like events	TVS, input filtering	Short & fast → TVS first
Load Dump (+ high energy)	Long positive surge, high energy	Battery disconnect while charging	High-power TVS + eFuse shut-off (or clamp+limit)	Size TVS for energy; check eFuse SOA/heat

Reverse, Jump-start & Power Path ORing

Reverse-current blocking: back-to-back FET eFuse prevents backfeed during power-mux and power-down.
Jump-start: pick a high-voltage eFuse + TVS; avoid relying on series diode drop only.
ORing: ideal-diode controllers minimize drop; eFuse adds limits/OVP/telemetry.
Verification: perform downstream-driven-high sink-current tests to confirm reverse blocking.

Thermal & Layout — R_DS(on)·I² and ΔT estimate

Conduction loss P_cond ≈ I_rms²·R_DS(on). When clamping, add P_clamp ≈ (V_IN−V_clamp)·I averaged over time. Temperature rise: ΔT ≈ (P_cond + P_{transient,avg})·θ_JA.

Example: I = 3 A, R_DS(on) = 40 mΩ → P ≈ 0.36 W. If θ_JA = 50 °C/W → ΔT ≈ 18 °C (add copper/thermal vias).

Use large copper pours and 6–12 thermal vias on the exposed pad to inner/ground planes.
Prefer thicker copper / multi-layer spreading; keep high-current paths short and wide.
Place bulk caps near the eFuse; consider an RC snubber for harness ringing.

See dv/dt to manage inrush and reduce nuisance trips; for high-current boundaries, check the comparison section.

Engineer’s checklist

Size the TVS for ISO spikes/load-dump energy; pick eFuse VIN rating & OVP strategy (clamp/shut-off).
Select AEC-Q100 grade & temperature range; prepare COC, Date Code, AEC-Q100, RoHS/REACH docs.
Use back-to-back FET eFuse for reverse/backfeed protection; validate with sink-current tests.
Estimate P = I²·R and ΔT; reinforce copper/vias accordingly; verify at hot/cold/low VIN.
For persistent surges, favor shut-off; for brief spikes, use clamp + TVS (see protection functions).

Request AEC-Q100 small-lot samples → Cut-tape / partial reels · COC & Date Codes included

USB-C / Port Power — eFuse Protection for VBUS

For USB-C eFuse protection, pair a TVS with an eFuse to manage inrush, OVP clamp/shut-off, and reverse-current. Proper ILIM and dv/dt settings balance heat, cost, and stability.

What matters on USB-C VBUS

VBUS transients — plug/unplug and cable inductance create spikes: the TVS absorbs energy, the eFuse handles inrush control and fast OVP clamp/shut-off.
Reverse-current — in bidirectional/battery systems the system can backfeed into Type-C. Use a back-to-back FET eFuse and perform “downstream-driven-high” sink-current tests.
OVP set-point — 5 V sinks often target ~6–7 V; with PD 9/12/15/20 V, require adjustable/wide-range OVP with ~10–15% headroom. Large-energy events favor shut-off over long clamp.
ILIM vs heat/cost — higher ILIM avoids adapter OCP trips but raises I²R loss; lower ILIM cuts heat yet may cause PD renegotiation. Coordinate with dv/dt soft-start.

Three practical “port recipes”

Sink · 5 V Only

Low-voltage eFuse with dv/dt, ILIM, reverse-block
OVP ≈ 6–7 V + SMBJ/SMF TVS near connector
Limit I_peak to ease cable/connector stress (calculator)

Sink · PD up to 20 V

High-voltage eFuse (wide OVP, fast shut-off), back-to-back FET
PD controller drops/turns off before re-enabling the eFuse on profile change
Use TVS + shut-off for large-energy surges

DRP / Bidirectional (with battery)

Use true bidirectional/back-to-back eFuse
Prevent battery/system backfeed to cable
Ideal-diode controller for low-drop ORing; eFuse adds protection/limits

ILIM & dv/dt — system impact

ILIM too high: higher I²R heat; more risk of thermal shutdown during faults.
ILIM too low: start-up fails or PD re-negotiates repeatedly; lengthen ramp t_r to reduce I_peak.
Guideline: ILIM ≥ adapter steady current × 1.2–1.5; then validate thermal and measurement window (see dv/dt).

Engineer’s checklist (USB-C VBUS)

Place a TVS at the connector; size for clamp voltage & energy.
Choose eFuse with back-to-back FET, adjustable OVP/ILIM; wire PG/FAULT to the PD controller.
Set OVP headroom per profile (5 V→6–7 V; PD levels +10–15%). Prefer shut-off for large-energy events.
Estimate I²R and ΔT; lower R_DS(on) reduces heat but may raise cost—find balance.
Test “downstream-driven-high” reverse blocking and plug/unplug transients; state the sampling window.

More on inrush & dv/dt and OVP/reverse-current behaviors. For high-power boundaries, see the comparison section.

USB-C VBUS path: connector → TVS → eFuse (ILIM, OVP clamp/shut-off, reverse-current blocking) → bulk cap/load; PD controller ties to EN/FAULT — USB-C VBUS with TVS + eFuse: manage inrush, **OVP**, and **reverse-current**.

Cross-Brand eFuse Alternatives — Unified Comparison

Quick matches for popular parts (e.g. tps2595 alternative) with unified engineering fields: VIN/OVP, ILIM mode, RDS(on), I_CONT, reverse-block, I²C/PG, AEC-Q100, package, and application tags.

Filter by scenario → compare unified fields → jump to PN pages or submit BOM.

Cross-brand eFuse comparison — ✔︎ strong · ○ limited · — none
Part	Brand	VIN / OVP	ILIM mode	RDS(on) typ [mΩ]	I_CONT [A]	Reverse-Block	I²C / PG	AEC-Q100	Package	Application tags	Small-lot
TPS2595	Texas Instruments	Low-mid VIN · Adj OVP (Clamp/Shut)	Constant / Foldback (config.)	— (see DS)	— (see DS)	✔︎ Back-to-Back FET	PG ✔︎ / I²C ○	○ (variant-dep.)	DFN/QFN	SSD · USB-C · General rails	Cut-tape / Partial reel
TPS26600	Texas Instruments	Wide VIN (to ~60 V) · OVP options	Const./Foldback/Hiccup (config.)	— (see DS)	— (see DS)	✔︎ Reverse-Block	PG ✔︎ / I²C ○	✔︎ (variant-dep.)	HTSSOP/QFN	Industrial · 12/24 V auto	Lead-time compare
MAX17525	Analog Devices / Maxim	Wide VIN (to ~60 V) · OVP config.	Const./Foldback (family-dep.)	— (see DS)	— (see DS)	✔︎ Reverse-Block	PG ✔︎ / I²C ○	○ (variant-dep.)	TQFN/QFN	Industrial · Telecom	Cut-tape options
NIS5021	onsemi	12/24 V focused · OVP/UVLO	Constant / Foldback (family)	— (see DS)	— (see DS)	○ / ✔︎ (by variant)	PG ✔︎ / I²C —	○ (variant-dep.)	SOIC/QFN	Automotive · General 12 V	Stock-check
STEF12	STMicroelectronics	12 V class · OVP options	Const./Foldback (family)	— (see DS)	— (see DS)	✔︎ Reverse-Block	PG ✔︎ / I²C —	○ (variant-dep.)	DFN/QFN/SO	Industrial · Consumer	Lead-time compare
Renesas (family)	Renesas	5–24 V / Wide VIN options	Const./Foldback/Hiccup (by PN)	—	—	✔︎ (variants)	PG / I²C (by PN)	✔︎ (selected)	QFN/DFN	USB-C · 12/24 V	Submit BOM
Microchip (family)	Microchip	5–24 V (family-dep.)	Const./Foldback (by PN)	—	—	✔︎ / ○ (by PN)	PG / I²C (by PN)	○	DFN/QFN/SO	Consumer · General	Stock-check

Notes: Specs vary by variant—always verify in the official datasheet. Clamp vs shut-off behavior impacts heat/continuity (see protection functions).

Top queries — quick cross-matches

TPS2595 alternative

ST STEF12 — Reverse-block, PG
onsemi NIS5021 — 12 V class
ADI MAX17525 — Wide VIN option

TPS26600 alternative

ADI MAX17525 — Wide VIN
ST STEF12 — 12/24 V rails
onsemi NIS5021 — 12 V domain

MAX17525 alternative

TI TPS26600 — Wide VIN peer
ST STEF12 — Mid-VIN option
onsemi NIS5021 — 12 V class

onsemi NIS5021 alternative

TI TPS2595 — Low-mid VIN
ADI MAX17525 — Wide VIN
ST STEF12 — 12 V domain

Rule #1 — Match the feature set first

Align Reverse-Block, OVP strategy (Clamp/Shut-off), ILIM mode, and I²C/PG. Then compare RDS(on) & I_CONT.

Rule #2 — Pin-compatible ≠ drop-in

Verify EN/PG/ILIM polarity and OVP setting method before layout reuse. See pin-to-pin notes.

High-energy surges may prefer shut-off vs long clamp (thermal). For wide VIN industrial/automotive rails, wide-range parts can improve robustness (see automotive).

See pin-to-pin notes → Submit BOM for cross-match →

Pin-to-Pin Replacement Maps — Check Pin Functions, Polarities & Methods

Before a pin compatible eFuse swap, verify EN/ILIM/PG polarities and OVP/UVLO setting methods. “Footprint compatible” often still needs resistor or wiring tweaks.

QFN 5x5 eFuse pin map: VIN, VOUT, ILIM, OVP/UV, EN, PG/FAULT, GND, exposed pad — QFN 5×5 typical map (back-to-back FET): VIN/VOUT, EN, ILIM, OVP/UV, PG/FAULT, EPAD.

DFN 3x3 eFuse pin map with ILIM/EN/PG differences and exposed pad — DFN 3×3 compact map (single or simplified FET): pay attention to ILIM/EN/PG pins.

✅ Same pins & polarities → drop-in ⚠️ Pinout ok but polarities/methods differ → minor edits ⛔ Critical signal differs → layout change

Pin compatible eFuse / footprint compatible quick map — verify datasheets before reuse
Source PN	Target PN	Package / Footprint	Gate Topology	EN polarity	PG/FAULT logic	ILIM setting	OVP method	UVLO method	Reset default	Thermal Pad	Footprint Compatible?	Notes (≤10 words)
TI TPS2595	ST STEF12	QFN/DFN 3×3 class	Back-to-Back FET	High (typ.) / pull-down EN	Open-drain PG (low active)	R-set / pin-strap	Adjustable clamp / shut-off	Fixed / divider (family)	Auto-retry (config.)	EPAD to GND copper	⚠️	Check PG polarity & OVP net
onsemi NIS5021	ADI MAX17525	QFN/TQFN 4×4 class	Back-to-Back FET	High (typ.)	Open-drain PG / FAULT	R-set (variant dep.)	Clamp/shut-off options	Fixed / adjustable (family)	Latch or auto-retry	Large EPAD, vias 6–12	⚠️	Confirm EN pullups & UVLO
TI TPS26600	ST (wide-VIN alt.)	HTSSOP/QFN footprint diff.	Back-to-Back FET	High (enable)	PG open-drain (typ.)	R-set / strap / hiccup cfg.	Clamp &/or shut-off	Adjustable (divider)	Auto-retry (cfg.)	EPAD to GND plane	⛔	Footprint not same family

Legend — ✅ drop-in; ⚠️ minor edits (resistors/wiring); ⛔ layout change. Always re-check official datasheets.

EN & PG/FAULT differences

EN active-high/low varies; PG/FAULT may switch from open-drain to push-pull. Add pull-ups / series resistors, or invert in the MCU if needed.

ILIM / OVP methods

ILIM may move from resistor-set to pin-strap / I²C; OVP from fixed threshold to adjustable. Confirm divider values and the default Clamp vs Shut-off (see protection functions).

Single vs Back-to-Back

Reverse-current behavior differs. If the board already uses ideal-diode/ORing, evaluate the whole path when swapping (see comparison).

Layout tips

Thermal pad & vias: tie EPAD to large copper; add 6–12 thermal vias.
Sensing nodes: place ILIM/OVP/UVLO dividers close to the IC; clean ground; avoid high-current returns.
VIN/VOUT routing: short & wide; keep away from PG/FAULT/EN traces.
Trial first: use jumpers / 0 Ω to validate differences before final layout.

Pick candidate PN in #alternatives.
Use this map to check polarity/setting/reset differences.
Not sure? Send us your schematic/layout for a pinmap review.

Ask pinmap review → See footprint notes & submit BOM →

FAQ — Quick Answers & Deep Links

One-line answers to common questions, with Read more links to section anchors and a short OTP/eFuse disambiguation.

Basics

What is an eFuse (meaning)?

An eFuse is an electronic fuse IC that protects a power path. Read more → #intro

What is the eFuse principle?

Detect faults → limit/shut off → reset safely. Read more → #how-it-works

Is an eFuse an IC or a fuse?

It’s an IC using MOSFETs and control logic to provide resettable protection. Read more → #intro

What are eFuse characteristics?

ILIM, OVP, UVLO, dv/dt, reverse-block, PG/FAULT, optional I²C. Read more → #functions

What is eFuse memory / OTP vs power eFuse?

OTP eFuse stores one-time bits; power eFuse protects supply rails. Read more → OTP blog

Compare & Selection

eFuse vs MOSFET (discrete)?

eFuse integrates protection; discrete MOSFET needs external control. Read more → #compare

eFuse vs load switch?

Load switches give simple on/off; eFuses add precise protection. Read more → #compare

eFuse vs hot-swap controller?

High-power hot-plug prefers hot-swap + external FET SOA. Read more → #compare

eFuse vs PTC / fuse?

eFuses trip fast and resettable; PTC/fuse are slow and coarse. Read more → #compare

eFuse vs HSD (high-side driver)?

HSD drives loads; eFuse protects rails and power paths. Read more → #compare

Behavior & Tuning

What sets eFuse inrush (dv/dt)?

I_peak = C·dV/dt; slower ramps cut inrush peaks. Read more → #dvdt

OVP clamp vs shut-off?

Clamp keeps output alive; shut-off minimizes heat load. Read more → #functions

What is reverse-current blocking?

Back-to-back FETs stop backfeed and power-mux cross-talk. Read more → #functions

Constant, foldback, or hiccup?

Constant is smooth; foldback lowers heat; hiccup minimizes average heat. Read more → #functions

How to set ILIM safely?

Target ≥ adapter steady current ×1.2–1.5 with ramp control. Read more → #dvdt

Automotive & Interface

Is there an AEC-Q100 eFuse?

Yes—select grade/temperature and verify declarations. Read more → #automotive

Can eFuses handle ISO 7637 / Load Dump?

TVS + eFuse co-design is required; long energy favors shut-off. Read more → #automotive

Is eFuse useful on USB-C VBUS?

Yes—for inrush, OVP, and reverse-current with a TVS. Read more → #usb

Disambiguation

What is Knox eFuse?

A phone SoC’s OTP eFuse flag, not a power-path eFuse. Read more → OTP blog

How many eFUSEs does Xbox 360 have?

Refers to SoC eFUSE rows, unrelated to power eFuses. Read more → OTP blog

Is EEPROM the same as eFuse memory?

No—eFuse is one-time programmable; EEPROM is rewritable. Read more → OTP blog

Need part picks or replacements? See cross-brand alternatives and pin-to-pin maps.

Small-lot eFuse (1–1000 pcs). Cut-tape & partial reels.

Pin-to-pin alternatives. 48-hour quote with lead-time compare & risk notes.

Low MOQ
Pin-to-pin & cross-brand
Cut-tape / Partial reels
48h quote

Get 48-hour Quote → See Cross-Brand Alternatives Pin-to-Pin Notes

Small-lot eFuse (1–1000 pcs). Cut-tape & partial reels.

Buy Scenarios — pick your path

Pick your scenario and we’ll provide fast routes for in-stock, alternatives, and document packs with risk notes (eFuse sample · automotive eFuse sample · 12V eFuse · USB-C eFuse).

Small-lot eFuse buy scenarios: 1–50 urgent repair, 100–300 pilot second-source, AEC-Q100 automotive sample — Choose your path → get stock signals, one equivalent, second-source sets, or AEC-Q100 document packs.

A | Urgent repair / spares 1–50 pcs

Need: nearby stock + one pin-to-pin equivalent (or minimal rework).

Check in-stock signals (cut-tape / partial reels).
Provide one equivalent as a fallback.
Go straight to Quick Quote (you can enter just 1–3 MPNs).

Risk notes: confirm EN/PG polarities and OVP thresholds (see #pinmap / #functions).

Get quick quote → See one equivalent

B | Pilot run 100–300 pcs

Need: build a second-source set (primary PN + backup).

In the cross-brand table, tick: Reverse-Block / Low RDS(on) / USB-C / 12V.
Narrow to 2–3 candidates; verify differences via the Pin-to-Pin Map.
Submit the BOM; within 48h we return lead-time comparison + risk notes.

Risk notes: Clamp vs Shut-off affects heat and continuity (see #functions).

Build second-source set Submit BOM →

C | Automotive prototype AEC-Q100

Need: AEC-Q100 only with a document pack (COC / Date Code / AEC-Q100 / RoHS / REACH).

Read the Automotive guide (TVS + eFuse co-design).
Tick in the cross-brand table: Automotive (AEC-Q100) / Wide VIN.
In the BOM, select Grade (0/1/2); we’ll return candidates and a document pack by grade.

Risk notes: for ISO 7637 / load dump, we recommend TVS + Shut-off/Clamp synergy (see #automotive).

Request AEC-Q100 samples → See automotive picks

USB-C eFuse 12V rail 24V / industrial Reverse-Block Low RDS(on) I²C / PG Wide VIN Automotive eFuse sample

Within 48 hours: lead-time comparison + alternatives + pin-compatibility verdict + risk notes (OVP / ILIM / EN / PG). Need 1–1000 pcs? Submit BOM →

Seven-brand eFuse shortlist — easy to buy / replace / footprint

Fast shortlist across seven eFuse brands: prioritize “easy to buy / easy to replace / easy footprint,” with 3–5 picks per card + one cross-brand starting point (links to programmatic PN pages).

Quick shortlist → jump to PN pages or alternatives.

Texas Instruments (TI)

Easy to buy · Easy to replace · Easy footprint

Common packages, broad families, thorough documentation — good for small-lot and second-source.

TPS2595
VIN/OVP: family-dep. · ILIM: const/fold (cfg) · Reverse-block: BTB · Package: DFN/QFN
TPS2596
VIN/OVP: see DS · ILIM: cfg · Reverse-block: BTB · Package: QFN
TPS26600
Wide VIN class · ILIM: const/fold/hicc (cfg) · Reverse-block: BTB · Package: HTSSOP/QFN
TPS25940
VIN/OVP: see DS · ILIM: cfg · Reverse-block: BTB · Package: QFN

tps2595 alternative: start with ST STEF12 → see cross-brand table · pin-map notes.

Get 48h quote →

STMicroelectronics (ST)

Easy to buy · Easy footprint

Covers 12 V / USB-C scenarios; common packages; complete documentation.

STEF12
12 V class · ILIM: family-dep. · Reverse-block: BTB · Package: DFN/QFN/SO
STEF01
VIN/OVP: see DS · ILIM: cfg · Package: SO/DFN
STEF05
5 V class · ILIM: cfg · Reverse-block: family-dep. · Package: DFN/SO
STEF215
Dual rail (family) · Details: see DS · Package: QFN

st efuse alternative: TPS2595 peers → cross-brand table.

Get 48h quote →

onsemi

Easy replacement · Automotive options

Suited for 12/24 V rails and industrial scenarios; broad family coverage.

NIS5021
12/24 V focus · ILIM: family-dep. · Reverse-block: variant-dep. · Package: SO/QFN
NIS6131
VIN/OVP: see DS · ILIM: cfg · Package: QFN
NIS546x (family)
Wide VIN options · ILIM: cfg · Package: family-dep.

onsemi efuse alternative: peers for NIS5021 → ADI MAX17525.

Get 48h quote →

Analog Devices / Maxim (ADI)

Wide VIN · Industrial

Wide-voltage, common for industrial and telecom power; well-documented.

MAX17525
Wide VIN class · ILIM: const/fold (family) · Reverse-block: BTB · Package: QFN/TQFN
LTC4368 (controller)
Ideal diode + protection controller · Ext. FET · Package: MSOP/QFN
MAX176xx (family)
Family options · ILIM/OVP: see DS · Package: QFN

Cross-brand: MAX17525 ↔ TPS26600.

Get 48h quote →

Renesas

Automotive options · Broad family

Wide VIN / AEC-Q100 options; good for 12/24 V rails and industrial.

Family pick #1
VIN/OVP: wide options · Reverse-block: BTB (by PN) · Package: QFN
Family pick #2
Details: see DS · Package: family-dep.
Family pick #3
Automotive options · Package: QFN/HTSSOP

Cross-brand: Renesas wide-VIN ↔ onsemi NIS series.

Get 48h quote →

Microchip

Common packages · Stable supply

Rich power-distribution/protection lineup; suited for 5–12 V rails in consumer/industrial.

Family pick #1
5–12 V focus · Reverse-block: by PN · Package: SO/QFN
Family pick #2
ILIM/OVP: see DS · Package: DFN/QFN
Family pick #3
Low RDS(on) options · Package: family-dep.

Cross-brand: Microchip 12 V rail ↔ ST STEF12.

Get 48h quote →

Diodes Incorporated

Cost-effective · Common packages

Good for cost-sensitive, common-package replacements; easy for small-lot deployment.

Family pick #1
USB-C / 5 V focus · Package: DFN/QFN
Family pick #2
12 V rail options · Package: SO/QFN
Family pick #3
Reverse-block: by PN · Package: family-dep.

Cross-brand: Diodes DFN/QFN ↔ TI TPS259x family.

Get 48h quote →

Notes: fields above summarize family/common traits; always refer to official datasheets for specifics. Clamp vs Shut-off behavior affects thermal and continuity (see #functions). For pinout and polarity differences, see #pinmap.

See full cross-brand table Get 48h quote →

Lead-time compare (48h) · No mixed lots · COC & Date Code · MSL dry-pack · Counterfeit control SOP

Submit BOM → See alternatives

Lead-time — three paths

In-Stock

Ship today / next day (multi-warehouse, nearest origin)
Cut-tape / Partial reel supported (see fee policy)
Stock can be held 48h (subject to confirmation)

Check availability →

Second-Source

48h cross-brand lead-time comparison
Mark pin-to-pin compatibility & risks (EN/PG/OVP/ILIM)
Best for pilot runs 100–300 pcs

Build options

Buildable

Factory / build schedule (weeks)
Staged shipments supported (scheduled)
Transparent MOQ/MPQ rounding policy

Request schedule →

Path	Availability signal	Typical lead time	Cut-tape / Partial reel	Repack (if any)	Best for	Notes
In-Stock	Multi-warehouse / hold 48h	Same/next day	Yes — see cut tape fee policy	No (factory reel preferred)	Urgent repair 1–50	COC & date code provided
Second-Source	Cross-brand peers	48h compare + ETA	Likely yes	No / Minimal	Pilot 100–300	Pin-to-pin & risk notes
Buildable	Factory build slots	Weeks (scheduled)	Factory full reel	N/A	Planned batches	MOQ/MPQ rounding disclosed

Tip: quote the three paths in parallel — deliver with a mix of fast and scheduled orders.

Price & packaging transparency

Cut tape fee

Charged by threshold; bundle-waive / fee cap supported (subject to PO confirmation).

Partial reel

Partial reels supported; keep labels and inner core (if applicable) and mark remaining quantity.

No mixed lots

No mixed lots within one PO; multiple date codes only with prior consent.

COC / Date Code

Provided by default via shipment/email; automotive orders can add an AEC-Q100 statement.

MSL / ESD

Desiccant + humidity card + vacuum bag; label MSL level & open-time; bake and re-seal if needed.

Counterfeit control & QA

Counterfeit control SOP for eFuse: sourcing, inspection, x-ray, test, dry-pack — SOP: sourcing → visual/labels → microscopy/X-ray → parametric sampling → dry-pack sealing.

Source traceability: prioritize authorized/trusted channels; keep purchase records (available on request).
Appearance / label verification: logo/marking/reel/box SN consistency.
Package & leads: microscopy for moisture, oxidation, sanding marks.
Random sampling (as needed): ILIM/UVLO/OVP typical ranges & protection response.
X-ray (optional): internal structure consistency (family comparison).
Dry re-seal: bake per MSL level, then vacuum with HIC.