Glitch Filters & Window Detectors for Stable Power

Time-constant glitch filters and window comparators reject narrow blips and certify “voltage ready” windows. In multi-rail systems, PG, resets, and supervisors can chatter during ramps and cross-loads. These helpers shape signals by blocking sub-microsecond spikes, adding hysteresis, and enforcing a valid window before downstream enables or resets are released.

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Who This Is For & How We Help

Hardware/validation engineers & PI owners: care about threshold accuracy, propagation delay, and minimum pulse rejection.
Firmware leads: focus on PG/Reset de-glitch and start-up sequencing; prefer clarity on open-drain vs push-pull outputs.
Small-batch purchasers: look for AEC-Q100 grades, packages, lead time/alternatives, and cross-brand candidates for quick validation.

Primary conversion: Submit your BOM (48h cross-brand options).

Secondary conversion: Ask an engineer (short form) — place at the end of Validation Playbook. Positioning: neutral, engineering-first; emphasize multi-brand alternatives and AEC-Q100 availability with measurable specs (mV, %, µs).

Introduction & Search Intent

Solves: chattering PG, false “voltage ready,” brown-out bounces, POR oscillation, and downstream LDO/controller false starts.
Typical positions: at PG pins; at supervisor outputs; between analog comparators and digital logic; at enable pins of DC/DCs, PMIC rails, or load switches.

When to Use Glitch Filters vs Window Detectors

Glitch Filter

Cleans a single-threshold line (PG, reset, PGOOD) by enforcing minimum pulse width and minimum stable time. Ideal in digital logic paths to stop sub-µs blips from reaching downstream enables or resets.

Window Detector

Certifies a rail stays inside [V_LO, V_HI] for a hold time t_hold before asserting “valid,” with hysteresis on both edges. Best for analog domains such as ±5% windows, ADC references, and sensor rails where accuracy matters.

Decision Matrix (Quick Guide)

Edge model: Single-edge cleanup → Glitch; Dual-edge/window certification → Window.

Accuracy: Tight ±2–5% threshold → Window; Basic logic de-glitch → Glitch.

Latency budget: RC/digital filter delay acceptable → Glitch; Comparator + hysteresis delay acceptable → Window.

Use cases: PG/Reset pulse debouncing → Glitch; ADC ref & ±5% sensor rails → Window.

I/O stage: Open-drain bus OK → both; Require push-pull/defined polarity → pick by device family.

Supply/common-mode: Wide common-mode & temp drift control needed → Window preferred.

Rule of thumb: Enforce a minimum pulse width/stable-time on PG/Reset → choose a glitch filter. Require a rail to remain inside [V_LO, V_HI] for t_hold with dual-edge hysteresis → choose a window detector.

Avoid solely using RC filters to certify “voltage ready” on slow ramps or brown-out rebounds—use a proper window when ±% accuracy is critical. Always verify system-level propagation delay against downstream sequencing.

Architectures & Signal Paths

Digital/RC Time-Constant Filters

Forms: RC + Schmitt trigger, monostable (one-shot), retriggerable monostable. Strengths: simple BOM, tunable minimum pulse width/stable-time. Cautions: t_MIN depends on R/C tolerance & temperature; added propagation delay must fit sequencing; slow ramps and bounce need validation.

RC glitch filter: PG_IN has narrow glitches; the RC node smooths; Schmitt output rejects blips and preserves valid edges. — RC + Schmitt imposes a minimum pulse width so narrow blips never reach logic.

Analog Comparator Windows

Structure: two comparators + resistor ladder (V_LO, V_HI) or integrated window comparator with dual-edge hysteresis. Why: percent-grade accuracy for analog domains (±x%), explicit hold-time before “valid”. Watch-outs: comparator input bias/leakage ≪ ladder current; propagation-delay spread & temp drift enter the error budget.

Window detector: resistor ladder defines V_LO and V_HI; dual comparators assert valid only when the rail stays inside the band with hysteresis. — Window comparators certify the band [V_LO, V_HI] and add dual-edge hysteresis.

Supervisor-Class Devices vs Discrete Networks

Supervisor-class: factory-trimmed thresholds, tight tolerance, small delay spread, short signal paths, small BOM; flexibility tied to vendor options.
Discrete comparator + ladder: fully configurable windows/hysteresis/domains; higher sensitivity to R/Ref tolerance and input bias; more validation effort.

Automotive Considerations

Prefer AEC-Q100 parts (correct grade) with wide supply/common-mode, robust ESD, and characterized behavior on slow ramps and brown-outs. Validate across temperature extremes and cranking; ensure output stage (open-drain/push-pull) and pull-ups are safe within system domains.

Design Rules & Sizing Recipes

Glitch Filter — RC Time Constant

Choose R·C so worst-case PG bounce (rise & fall) keeps the filter node below V_TH (no false trigger). Use the working estimate t_MIN ≈ −R·C·ln(1 − V_TH/V_STEP). Include tolerance stacks for R, C, V_TH, and temperature; add ~20–30% margin after corner analysis.

Window Ladder — V_LO / V_HI

Set V_LO = V_NOM(1 − x%) and V_HI = V_NOM(1 + x%); choose resistor ratios accordingly. Ensure comparator input bias ≪ ladder current (e.g., I_bias ≤ 1% · I_ladder). Add ladder TCR and V_REF drift to the overall threshold tolerance.

Hysteresis Target

Set ΔV_HYS ≥ (2–3) × the maximum ripple at the comparator input to avoid chatter. With positive feedback, a quick rule is ΔV_HYS ≈ I_FB · R_FB; validate both edges across temperature corners.

Propagation Delay Budget

Make sure the “rail-good → dependent converter enable” path (filter + comparator + logic) fits the sequencing order and inrush margins. If necessary, increase t_hold or advance upstream PG to preserve timing headroom.

Open-Drain vs Push-Pull

Open-drain: choose pull-up for bus fan-out and edge rate (rise-time vs power); use level shifting across domains. Push-pull: best for tight timing, but check domain tolerance and backfeed paths when crossing supplies.

Minimum pulse rejection and propagation delay: narrow pulse below t_MIN is rejected; wide pulse passes with t_PD to the output. — Narrow pulses below t_MIN are rejected; accepted pulses appear after propagation delay t_PD.

Timing & Math Cheat-Sheet

Minimum Pulse Rejected

t_MIN ≈ −R·C · ln(1 − V_TH/V_STEP)

Define V_STEP at the filter node (effective step seen by the RC) and V_TH as the Schmitt/comparator threshold. Check both rising and falling edges. After cornering tolerances, add ~20–30% margin.

Tolerances: R/C tolerance & tempco, threshold drift, supply variation. Re-evaluate if the upstream edge is slew-limited (finite dV/dt).

Window Comparator Thresholds (3-Resistor Ladder)

V_LO = V_REF × R_bottom / (R_top + R_bottom)
V_HI = V_REF × (R_bottom + R_mid) / (R_top + R_mid + R_bottom)

Choose ladder ratios for V_LO=V_NOM(1−x%) and V_HI=V_NOM(1+x%). Ensure comparator input bias is much smaller than ladder current (e.g., I_bias ≤ 1% · I_ladder) so thresholds do not shift.

Include tolerances (R TCR, V_REF ppm/°C, comparator offset). Recommended: quick Monte-Carlo with temperature steps to bound V_LO/V_HI spread.

Hysteresis via Feedback

ΔV_HYS ≈ I_FB · R_FB (or device-specific relation).

Target ΔV_HYS ≥ 2–3 × ΔV_RIPPLE at the comparator input. Budget extra headroom for expected undershoot/overshoot during transients. Verify both edges across temperature corners.

Larger hysteresis improves chatter immunity but increases release latency; check sequencing dependencies.

Quick Rules

Size RC from worst-case V_STEP and add 20–30% margin.
Keep I_bias ≤ 1% · I_ladder to protect threshold accuracy.
Set ΔV_HYS ≥ 2–3× ripple to guarantee chatter-free edges.
Account for comparator/logic propagation delay t_PD in the enable chain.

Validation Playbook

Bench Setup

Profiles: slow/fast ramps and brown-out dips; add load steps and injected ripple.
Measure: PG jitter, assert/deassert times, and false-trip rate.
Log: annotated waveforms with timestamps; repeat at cold/room/hot temperature points.

Sweep Cases

VIN ramp speed: e.g., 0.1 / 1 / 10 V·ms⁻¹.
Temperature: device corners (e.g., −40 / 25 / 85 °C or per grade).
Ladder tolerance: swap R bins by ±1/±2 to emulate production spread.
Noise injection: 10–100 mVpp, 10 kHz–2 MHz; observe window integrity and chatter immunity.

Pass Criteria

No PG chatter at min/max ripple levels.
Window asserts only while the rail remains inside [V_LO, V_HI] for t_hold.
Consistent release on down-ramp with hysteresis preserved.
False-trip rate below project limit (e.g., ≤10⁻⁶/s) and bounded worst-case scenario documented.

Need a quick review of your test plan? Ask an engineer (attach your scope captures).

Layout & EMI Notes

Comparator Inputs & Ladder

Keep comparator inputs short; route away from high dV/dt nodes. Add guarding/ring around sensitive nodes.
Place the resistor ladder close to the device; return its ground to a local star-point, not into power loops.
RC de-glitch networks should be near the source pin (PG/Reset). Shield the RC node from switch-node coupling.

Pull-Ups & PG Nets

Place pull-ups near the receiver. Avoid long, high-impedance PG lines; keep returns tight.
Keep debounced lines away from power switch edges. If ringing persists, add a small series R (50–200 Ω) plus C (100–470 pF) snubber.
For domain crossing, use defined polarity and check level shifting (open-drain + proper pull-up, or push-pull with tolerance checks).

EMI & Automotive Considerations

Prefer AEC-Q100 devices with wide supply/common-mode ranges and robust ESD.
Model slow power ramps and brown-out profiles; verify release/hold behavior across temperature.
Where needed, add ESD/EMI clamps at the input; re-run chatter tests with injected ripple.

IC Selection Guide (Engineer-Oriented)

Choose glitch filters for single-threshold PG/Reset lines where minimum pulse width and stable-time dominate. Choose window comparators/supervisors when a rail must remain inside [V_LO, V_HI] for a defined hold time with dual-edge hysteresis. Prioritize accuracy, propagation delay budget, input common-mode/supply range, output I/O type (OD/PP), and AEC-Q100 availability.

Accuracy & temp drift drive window/supervisor choices; RC-only filters are best for pulse cleanup.
Keep comparator input bias ≪ ladder current (target ≤1%·I_ladder); verify hysteresis ≥2–3× input ripple.
For small-batch builds, prefer cut-tape friendly packages and readily available grades.

Brand / PN	Function	Threshold Accuracy	Prop Delay / Min Pulse	Hysteresis	Sense / Supply	IO Type	AEC-Q100 & Temp	Package / Availability	Notes
TI TPS3702-Q1	Supervisor-style Window	High-precision (PN-dependent)	Typ/Max per DS	Internal (band options)	V_SNS/V_DD per DS	Open-drain / Push-pull (var.)	Yes / −40~125 °C	SOT-23-6; cut-tape friendly	Tight window; delay options
TI TLV6700-Q1	Window Comparator (dual comp + ref)	By ladder (ref accuracy per DS)	Comparator t_PD per DS	External FB sets ΔV	Wide CM; 1.8–18 V (typ)	Open-drain	Yes / −40~125 °C	SOT-23-6; cut-tape	Simple window builds with ladder
ST LM2903H / LM2903WH	Dual Comparator (discrete window)	By ladder (temp-graded)	Comp t_PD per DS	External FB sets ΔV	Wide CM / Supply per DS	Open-collector	Automotive variants	SO/THN; broad stock	Low-cost window via ladder
Renesas ISL88001 / 2 / 3	Voltage Supervisor	±~1–2% variants	Fixed delay options	Internal (device-dep.)	Sense vs V_DD per DS	OD / PP options	Grades available	SOT/SC; cut-tape	Low Iq; compact BOM
onsemi NCV308	Voltage Supervisor (auto)	PN-specific	Programmable delay	Internal	Per DS	OD/PP variants	AEC-Q100 / −40~125 °C	SOT-23; cut-tape	Good for reset + delay
onsemi NCV33161	Voltage Monitor / Window (dual)	By ladder	Comp t_PD per DS	External FB	Per DS	Open-collector	Automotive	SO/TSSOP	Dual channel convenience
Microchip MIC841 / MIC842	Comp/Window-style Monitor	By ref/ladder	Fast comp; per DS	Internal / external	Wide CM / low Iq	OD/PP options	Grades vary	SOT-23; cut-tape	Glitch-resistant front-end
Microchip MCP1319 (AEC-Q100)	Voltage Supervisor	PN-specific (mV)	Fixed delay choices	Internal	Per DS	OD or PP	Yes / −40~125 °C	SOT-23; cut-tape	Automotive supervisor
NXP FS85 Safety SBC	System PMIC (with supervisors)	PMIC-grade	Programmable (PMIC)	Integrated	Multi-rail; per DS	Mixed (system)	Automotive	SBC pkgs	Good for multi-rail platforms
Melexis (see sensor PMIC range)	—	—	—	—	—	—	—	—	Primary focus on sensors; use others for window/supervisor

Populate numeric fields from datasheets during build. Verify package/grade availability for cut-tape orders. Check open-drain vs push-pull pin options and polarity before routing.

Need part-to-part alternatives or pin-compatible swaps? Submit your BOM (48h cross-brand options).

Brand Matrix — Seven Brands (Placeholders)

Texas Instruments (TI)

Window comparators & glitch filters; automotive variants where applicable.

Placeholders: [TI-PN-1], [TI-PN-2]

Notes: accuracy bands, delay options, OD/PP variants, AEC-Q100 selections.

STMicroelectronics (ST)

Schmitt/comp + ladder-based window families; supervisor/reset lines.

Placeholders: [ST-PN-1], [ST-PN-2]

Notes: low-cost discrete windows; automotive comparator variants available.

NXP

Supervisors/window functions in SBC/PMIC lines; system-oriented.

Placeholders: [NXP-PN-1], [NXP-PN-2]

Notes: multi-rail platforms, safety features, automotive focus.

Renesas

Precision comparators & supervisors with window capability.

Placeholders: [REN-PN-1], [REN-PN-2]

Notes: tight thresholds, low I_q, OD/PP options.

onsemi

Automotive comparators & window-detect / supervisor families.

Placeholders: [ONSEMI-PN-1], [ONSEMI-PN-2]

Notes: NCV automotive grades, programmable delays, reset logic.

Microchip

Low-power comparators & compact window/supervisor solutions.

Placeholders: [MCHP-PN-1], [MCHP-PN-2]

Notes: SOT-23 footprints, cut-tape friendly SKUs.

Melexis

Automotive supervisors/window detect (sensor-centric portfolio).

Placeholders: [MLX-PN-1], [MLX-PN-2]

Notes: lean discrete-window builds may be preferred for general rails.

Note: Actual series/PNs will be populated from vendor datasheets during build to meet the “100% real, no fabricated info” rule.

Buying Triggers & Small-Batch Notes

Pilot Run (20–50 pcs)

Mix standard & automotive temp grades for coverage.
Validate ladder tolerances & temp drift; record V_LO/V_HI spread.
Confirm ΔV_HYS ≥ 2–3× ripple; log assert/deassert timing.
Track false-trip rate across corners; capture worst-case scenario.

Single-Chip Window vs Discrete

Single-chip window/supervisor → tighter accuracy, smaller BOM, faster bring-up.
Discrete comparator + ladder → flexible & stock-friendly, but more validation and tolerance control.
Choose by accuracy band, availability, and bring-up schedule risk.

Cross-Brand Equivalents

Match by threshold accuracy (±%/mV), hysteresis band/program, t_PD.
Verify AEC-Q100 grade, temp range, and I/O type (OD/PP, polarity, leakage).
Prefer cut-tape friendly packages for pilot builds and quick swaps.

Need pin-compatible alternatives or a short-list per rail? Submit your BOM (48h cross-brand options).

Frequently Asked Questions

How much hysteresis is enough to stop PG chatter?

Size hysteresis at the comparator input to be at least 2–3× the peak ripple under worst load and temperature. Add budget for reference drift and component tolerance. Larger ΔV_HYS increases release latency, so re-check sequencing. Typical rails tolerate 1–3% of V_NOM as a practical range.

RC vs digital glitch filter—latency and tolerance trade-offs?

RC filters set t_MIN from R·C but drift with R/C tolerance and TCR; they’re simple and analog-friendly. Digital/monostable filters offer stable thresholds and delays, yet add fixed t_PD and require supply/logic constraints. Use RC near noisy analog nodes; use digital when tight timing repeatability matters.

Setting V_LO/V_HI for ±5% rails with ripple present

Start from V_LO=V_NOM(1−5%) and V_HI=V_NOM(1+5%), then add half the expected ripple as guard. Ensure I_bias ≤ 1%·I_ladder so thresholds do not shift. Run quick Monte-Carlo including R TCR, V_REF ppm/°C, and comparator offset to confirm yield across temperature.

Propagation delay vs downstream inrush and sequencing

Add filter t_MIN + comparator t_PD + logic t_PD into the “rail-good → enable” budget. Ensure the upstream rail’s hold time still precedes the dependent rail’s inrush window. If margin is tight, increase t_hold, reduce downstream soft-start slope, or move the enable point earlier in the sequence.

Implementing minimum-assert-time (t_hold) without a microcontroller

Use a monostable or an RC+Schmitt that stretches a valid level by t_hold. A quick estimate is t ≈ −R·C·ln(1−V_TH/V_STEP); include 20–30% guard after tolerances. Some supervisors provide configurable delay pins, avoiding analog drift and simplifying board-to-board repeatability.

Open-drain pull-up value for multi-fanout PG buses

Target a controlled rise time: R_PU ≈ t_r/C_BUS using the worst-case bus capacitance (lines + inputs). Example: C_BUS=50 pF, t_r=1 µs ⇒ R≈20 kΩ. Balance EMI (slower edges) vs latency (faster edges). Place the pull-up near the receiver and verify VOL margins at maximum sink current.

Avoiding false window passes during slow ramps

Use dual-edge hysteresis and enforce a t_hold before “valid.” Validate with slow brown-in profiles and injected ripple. If edges are too slow, add a small RC at the input to limit dV/dt, or promote to a supervisor IC that specifies behavior on ramped supplies and temperature extremes.

Window detect for bipolar/negative rails (–V): options

Use differential comparators or level-shift networks that bring the −V rail into a valid input common-mode. Check input bias vs ladder current and ensure the reference remains isolated. Prefer devices rated for negative inputs or choose a window comparator with stated CMR covering the application range.

Automotive cranking and brown-out survival tips

Validate at −40/25/125 °C with realistic cranking dips and recovery. Ensure window thresholds and ΔV_HYS avoid chatter; log false-trip rate. Use AEC-Q100 devices with wide supply and ESD ratings. If resets must persist, add hold-up capacitance or use supervisors with guaranteed delay across temperature.

Level-shifting window outputs across logic domains

With open-drain, pull up to the target domain and confirm VIH/VIL and leakage. With push-pull, ensure tolerance to the destination rail and block back-feeding. Account for added propagation delay through translators or clamps. Re-measure rise/fall times and verify polarity conventions in reset/PG aggregators.

Comparator input bias and ladder current sizing

Keep I_bias ≤ 1%·I_ladder so thresholds remain accurate. Compute I_ladder=V_REF/R_EQ and include worst-case bias drift, input leakage, and temperature. For low-power ladders, raise current only enough to dominate bias while controlling dissipation and noise pickup on long traces.

When to prefer supervisor-class window ICs over discrete comparators

Choose a supervisor-class window when accuracy, delay repeatability, startup behavior, and logging/fault pins matter. Discrete comparators with ladders are flexible and cost-effective but demand tighter validation, tolerance control, and EMI review. Supervisors often reduce BOM and bring-up time in multi-rail platforms.

EMI: why filters pass on a quiet bench but fail in chassis

In chassis, return paths, cabling, and SW-node radiation inject correlated noise the bench lacks. Repeat tests with chassis grounding, bundled cables, and ripple injection. Increase ΔV_HYS, shorten inputs, add series R + small C, and relocate ladders. Re-validate against the EMI spectrum and worst load transients.

Dual-rail correlation (tracking) with two windows

Combine two window-valid signals using AND/OR/majority voters per system policy. Track phase skew and tolerance stack; log which rail is last-arriving. For sequence-critical rails, gate enables with a small monostable that asserts only when both windows are valid for t_hold to suppress intermittent overlap.

Calculating minimum pulse rejection with component tolerances

Start from t_MIN ≈ −R·C·ln(1 − V_TH/V_STEP). Corner R, C, and V_TH with tolerance and temperature, then add 20–30% guard. If the upstream edge is slew-limited, re-derive using the exponential RC charge crossing V_TH. Validate with injected noise at frequencies near the loop bandwidth.

Tip: keep answers and lab evidence synchronized—attach annotated waveforms when routing PG/Reset decisions to safety reviews.