Ground Bounce & Rail Ripple Monitors

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Return to Hub: Power Integrity Helper ICs

Audience: Power/Hardware/Validation engineers, PI & compliance (automotive/industrial), and small-batch validation & cross-brand sourcing users.

Core value: Turn invisible return-path noise and rail ripple into measurable thresholds, events, and logs—enabling evidence-driven decoupling and layout fixes.

Introduction — What are Ground Bounce & Rail Ripple?

Intro cover: comparison of ground bounce (return-path shift) versus rail ripple on VOUT with packaging/via/loop-area notes — Ground bounce shifts the local reference through the return path; rail ripple rides on VOUT. Both impact margins and timing.

Ground bounce is the transient shift of the local ground reference caused by finite return-path impedance (package leads, vias, copper geometry). Rail ripple is the periodic or bursty voltage variation on the supply rail, driven by switching currents and PDN resonances. They couple via loop area, via count, and return convergence.

Why deploy a monitor instead of relying only on an oscilloscope? Monitors provide continuous observation, programmable thresholds, event logging, and remote alerts—turning intermittent PI problems into actionable evidence for layout and decoupling fixes.

Core metrics to capture

Peak-to-peak (Vpp) and RMS amplitudes to bound worst-case excursions.
Peak-hold envelope for rare spikes that escape average measurements.
Spectral peaks (kHz–MHz) to fingerprint topology and layout resonances.
Event counters with timestamps for rate and clustering analysis.
Statistical percentiles (P95/P99) to track reliability margins over time.

Signals to Monitor & KPI Mapping

Signals illustration: VOUT at load and regulator, ground return convergence point, sensitive analog/clock rails, and IO banks for SSN — Monitor the return-path convergence point, VOUT at the load, sensitive analog/clock rails, and I/O banks susceptible to SSN.

Primary signal objects

GND return near the convergence point (minimize added loop area).
VOUT at both regulator and load ends for delta comparison.
Sensitive analog/clock rails with tight jitter/SNR budgets.
I/O banks prone to simultaneous switching noise (SSN).

Metric mapping → design risks

Vpp thresholds (mVpp) → overshoot/ground-rebound risk to logic margins.
Spectral peaks (kHz–MHz) → PDN resonance & routing fingerprints.
Event density (events/hour) → reliability trends and derating needs.
Operating dependency → temperature, load, and mode (PFM/PWM) sensitivity.

Tip: tag each event with VIN, load step, mode (PFM/PWM), temperature. This enables percentile KPIs (P95/P99) and before/after comparisons for decoupling or layout changes.

Sensing — Topologies & Device Paths

Select a sensing path that fits the noise/ripple signature. Spiky ground-bounce events benefit from peak/envelope detection and fast comparators; spectral/percentile analysis benefits from ADC sampling with proper anti-aliasing. Remote loads often need differential Kelvin sense.

Window / Comparator

Hardware thresholds with hysteresis; optional peak-hold and pulse stretching for IRQ/PG.

Tune hysteresis to prevent chatter.
Front-end RC shapes response; avoid distorting the node under test.

ADC Sampling

Multi-rail voltage/current sampling with programmable thresholds, logs, and bus readout.

Effective BW = sampling rate + anti-aliasing filter design.
Use mode/temperature tags for P95/P99 statistics.

Envelope / Peak Detector

Diode or active rectifier with RC to capture rare spikes; combine with comparator/ADC.

Account for temperature and diode drop bias.
Discharge time constant defines “memory” of spikes.

Differential / Remote Kelvin

Low-offset differential amplifier for remote VOUT sampling; reduces common-impedance error.

Check input CM range, CMRR, bias and drift.
Keep front-end RC off the main loop stability path.

Isolation & Protection

Digital isolation for cross-domain links plus UVLO/backfeed protection to avoid reverse influence.

Consider propagation delay for event alignment.
ESD/surge robustness and inrush limiting for long lines.

Selection keys

Input range & CMRR; headroom vs common-mode.
Effective bandwidth: sampling rate + RC/anti-aliasing combo.
Noise/reference grounding: AGND vs PGND strategy.
Hysteresis & debounce: constants for chatter-free alerts.
Alert type: PG/INT/IRQ assert/hold/clear rules.
Bus & logging: I²C/PMBus, counters/black-box logs.
AEC-Q100 / temperature range when automotive.

Quick tips: spikes → peak/envelope + comparator; statistics/spectra → ADC + anti-aliasing; remote loads → differential Kelvin; cross-domain/automotive → isolation + UVLO + backfeed protection.

Placement — Probing & Layout

Placement guidance: monitor near return-path convergence, sample VOUT at load and control points, differential routing with shielding, and spring-ground probing — Short loops, clear ground reference, differential/shielded routing, and probing accessories that do not alter the node.

Place sensors to minimize added loop area and reference ambiguity. Compare the regulator-end vs load-end VOUT to see distribution losses, and reference your monitor to the intended ground bridge point to avoid misleading common-impedance artifacts.

Loop minimization & reference

Probe ground-bounce near the return-path convergence point.
Sample VOUT at the load and at the control point for delta insight.
Single bridge point between AGND and PGND.

Wiring, shielding, probing

Differential pairs, short and tight to the return path.
Shield if necessary; avoid routes near the SW node.
Use spring-ground probe tips instead of long ground leads.

Do-no-harm principle

Monitor input impedance ≫ node impedance; the monitor must not create a new pole/zero.
Place envelope/peak RC in the monitor branch, not directly on the primary node.
Validate stability after adding any RC or sense amplifier.

Validation checklist: (1) Load- vs control-point VOUT delta; (2) single AGND–PGND bridge verified; (3) probe spring-ground A/B test; (4) cable routing away from SW node; (5) remove front-end RC → confirm poles unchanged.

Measurement — Test & Validation Flow

Measurement workflow: frequency sweep, baseline/closed/open loop, load matrix including PFM/PWM, spike versus window triggers, and logging of peak/RMS/events with tags — Cover both time and frequency domains; compare baselines; exercise load matrix; use dual trigger modes; log with environmental/mode tags.

Frequency sweep: 10 Hz → ½ f_sw (extend to 10× f_c if needed) to identify PDN resonances and dominant envelopes.
Baseline & modes: record Baseline, Closed-loop, and Open-loop/Bypass responses for apples-to-apples Vpp/RMS/peak comparisons.
Load matrix: Light-load PFM / Mid-load / Heavy-load / Dynamic steps (rise/fall, step size, duty).
Trigger strategy: spike capture (peak-hold / pulse-stretch) vs fixed-window statistics.
Logging: Peak, RMS, Event count, duration, timestamp, plus tags: VIN, load, mode (PFM/PWM), temperature.

Sweep tips

Use narrow RBW around suspected resonances; broaden elsewhere.
Tag results by mode (PFM/PWM); do not mix statistics without labels.
Capture both Vpp and RMS to split transient vs continuous components.

Trigger tips

Spikes → peak-hold + pulse stretching to guarantee IRQ visibility.
Window metrics → fixed window (e.g., 10–50 ms) for RMS/mean/Vpp statistics.
Align both triggers to a common timeline for causality with PG/PLL/load steps.

Condition	VIN (Min/Typ/Max)	Temp (°C)	Mode (PFM/PWM)	Load	Metrics (Vpp/RMS/Events)
Light-load	Min / Typ / Max	-40 / 25 / 85	PFM	< 10%	—
Mid-load	Min / Typ / Max	-40 / 25 / 85	PWM	40–60%	—
Heavy-load	Min / Typ / Max	-40 / 25 / 85	PWM	> 80%	—
Dynamic steps	Min / Typ / Max	-40 / 25 / 85	PFM or PWM	ΔI, slew (rise/fall), duty	—

Pitfalls: (1) sampling too slow → miss spikes; (2) over-aggressive anti-aliasing hides risk; (3) mixing PFM/PWM data without tags; (4) monitor front-end RC altering the node response.

Thresholds — Setpoints, Debounce & Hysteresis

Threshold methodology from VOUT tolerance: split RMS/average and peak limits, apply debounce/integration, add hysteresis bands, and implement alert→log→derate/limit→soft recovery chain — Derive thresholds from system tolerance; separate continuous vs transient limits; stabilize alerts with debounce and hysteresis; define a safe protection chain.

From tolerance to thresholds

Start from system tolerance (e.g., ±3% of VOUT) and worst-case modes. Split into continuous (RMS/mean over a window) and transient (Vpp/peak-hold) limits, and maintain separate up/down setpoints per mode.

Transient limit example: Vpp = 2.0–3.0% × VOUT.
Continuous limit example: RMS = 1.0–1.5% × VOUT.
Per-mode tables for PFM vs PWM prevent false positives.

Debounce / Integration

RC / moving average / windowed counts / vote-based events.
Tune window (e.g., 2–5 ms) and counts (e.g., N=3 per 100 ms).
Goal: reduce false positives while preserving real faults.

Hysteresis

Prevent oscillation around thresholds with separate up/down bands.
Typical band: 10–30% of the threshold value.
Consider amplitude + time joint conditions for sticky noise floors.

Protection chain

Alert (PG/INT/IRQ) asserts per rules (rising, hold-off).
Log events (counters/black-box with timestamp + tags).
Derate / Limit / Cutout depending on severity and policy.
Soft recovery after minimum cool-down; limit retries (e.g., 3–5).

Pitfalls: treating light-load PFM as a fault; amplitude-only thresholds without duration/statistics; overly aggressive recovery that causes oscillatory behavior.

Telemetry — Bus & Logging Integration

Telemetry integration diagram: GPIO/PG for instant alerts, I²C/SMBus polling, PMBus thresholds and black-box logs; bandwidth throttling and timeline alignment with PG/PLL/load steps — Layer fast alerts with PG/IRQ, periodic reads via I²C/SMBus, and PMBus thresholds/logs. Throttle bandwidth and align timelines for causality.

Use a layered approach: hardware lines for immediate protection, a mid-speed control bus for routine reads, and PMBus-style registers for programmable thresholds, event counters, and black-box logs. Balance sampling rate and resolution against bus budget, and time-align telemetry with PG/PLL and load steps for root-cause analysis.

Interface	Primary use	Typical latency	Typical data
GPIO / PG / IRQ	Immediate alert & interlock	µs–ms	Assert/deassert, pulse-stretch, cause code
I²C / SMBus	Polled V/I/T & counters	ms–tens of ms	RMS/Vpp samples, event count, status
PMBus	Programmable thresholds & black-box logs	ms–hundreds of ms	Thresholds, hysteresis, event log with timestamps

Bandwidth & throttling

Rate vs resolution: raise sampling when event density increases; reduce during steady state.
Min interval: enforce a floor (e.g., ≥10 ms) between uploads to avoid bus contention.
Change threshold: report only when metrics drift > x% or after y seconds.
Batching: pack multiple samples per transaction with a shared timestamp base.

Time alignment: use a common tick for PG/IRQ, PLL/clock, and load steps. Log event_id, timestamp, and tags (VIN, load, mode, temp) to enable causality analysis.

Suggested log schema (CSV header)

ts,rail,metric,peak_v, rms_v, events, duration_ms, vin, load, mode, temp_c, action, notes

Mitigation — False Positives & Root Causes

Mitigation playbook for ground-bounce and rail-ripple: distinguish PFM, current-limit knee, and soft-start; fix SW-node coupling and loop area; tune filters; close loop via decoupling, return path, AVP, spread-spectrum — Diagnose the trigger mechanism, sanitize routing, right-size filters, and implement a prioritized fix list with clear exit criteria.

Not every alert is a fault. Separate legitimate transients from measurement artifacts, then fix the coupling path and tune filters without hiding risk. Close the loop with decoupling, return-path adjustments, compensation/AVP, and spread-spectrum.

Scenario	Trigger mechanism	Mitigation
Light-load PFM	Burst envelope hits peak thresholds	Mode-aware thresholds; add debounce/hold-off; evaluate PWM-forced test
Current-limit knee	Limiting transition generates rebound	Soften knee; adjust step size/slew; add local bulk/AVP
Soft-start / hot-plug	Legit over/undershoot in startup window	Startup mask window; separate startup thresholds

Coupling & layout red lines

Keep sense routing away from the SW node; avoid broadside coupling.
Use differential, short, tight pairs hugging the return path; shield as needed.
Place Kelvin taps at the intended reference points; minimize loop area.
One AGND–PGND bridge; no hidden returns through shields or cables.

Filter trade-offs: excessive filtering conceals spikes; too little causes threshold chatter. Keep envelope/peak RC in the monitor branch, not on the primary node. Separate statistical windows from peak capture.

Closed-loop fixes (priority)

Decoupling: mix ESL/ESR, place close, stitch vias.
Return path: shorten loops; converge near load; add ground vias.
Compensation / AVP: speed recovery, control undershoot.
Spread-spectrum: reduce spectral peak clustering.

Exit criteria: Vpp/RMS/event-density all improve (≥30% recommended); dominant spectral peak reduces or broadens; P95/P99 improve with no new false positives; thresholds/hysteresis remain stable without over-relaxing.

Multi-Rail — Coordination & PG Aggregation

Phase interleaving

Stagger load steps and multi-phase angles across rails to avoid additive ground bounce.
For rails sharing returns, avoid simultaneous large di/dt windows.
Align monitoring clocks to the interleave pattern for cleaner causality.

PG aggregation logic

AND: strict interlock; all rails good → enable downstream.
OR: early warning to supervisory MCU; any rail breach → warn.
Majority vote: reduce single-rail false trips in noisy domains.
Normalize PG width using pulse stretching and add de-glitch time.

Upstream/Downstream sequencing

Upstream rail (e.g., 12V/5V) alert asserts → log + evaluate severity.
Downstream rails (core/IO) perform derate/limit with hold-off, not immediate reset.
After stabilization, coordinate recovery order; enforce minimum retry interval to avoid oscillation.

Automotive: During crank, relax undervoltage thresholds and widen hysteresis; for load-dump, provide fast over-voltage path (IRQ → limit/cutout) and soft recovery windows. Timestamp all actions with VIN/temperature tags.

IC Selection Guide — Monitoring & Supervision

IC selection matrix across seven brands covering window/peak/ADC detection, bus telemetry, logging, and automotive options — Shortlist of proven parts to instrument ground-bounce and rail-ripple, from comparators to PMBus telemetry and Kelvin front-ends.

Selection recipe

PFM false alarms → comparator with adjustable hysteresis + programmable debounce/integration.
High-frequency spikes → peak/ envelope path, front-end BW ≥ 5× f_sw.
Many rails, one brain → PMBus/SMBus aggregation + event black-box.
Automotive → AEC-Q100, wide temp, UVLO/OV/backfeed protections.
Remote loads → Differential Kelvin sense with high CMRR and low drift.

Brand	Family / PN	Input Range (V)	BW/Response	Detection	Threshold / Hyst.	Alerts	Bus	Logging	Iq	AEC-Q100	Notes
TI	INA233	Up to ~36 (see DS)	kHz-class ADC	ADC (V/I/Power)	Prog. limits	INT	I²C/PMBus	Counters/energy	Low	—	Multi-rail metering; black-box friendly
TI	INA226-Q1 / INA228-Q1	Up to ~36 / ~85 (DS)	kHz–100s kHz (DS)	ADC (V/I)	Prog. limits	INT	I²C / SPI	Counters	Low	Yes (-Q1)	Automotive current/voltage telemetry
TI	TPS3702	Logic-level (DS)	Comparator-fast	Window/Comparator	Hysteresis options	PG/RESET	—	—	nA–µA (DS)	—	Simple PG/voting bricks
TI	INA301	Sense amp range (DS)	Fast comparator path	Peak/Comparator	Prog. threshold	INT	—	—	Low	— / Q1 variants	Fast spike trip at knee/OC points
ST	TSC1641	Up to ~60 (DS)	kHz-class ADC	ADC (V/I/T)	Prog. limits	INT/PG (family)	I²C	Counters	Low	—	High-side metering AFE
ST	STM706 (family)	Logic-level (DS)	Supervisor-fast	Window/Reset	Fixed/opt. hyst.	RESET/PG/WDI	—	—	nA–µA (DS)	—	PG/reset bricks for logic domains
ST	STPMIC1	PMIC rails (DS)	Multi-rail mgr	ADC + PG	Prog. tables	PG/IRQ	I²C	Logs (hosted)	—	—	Processor PMIC with PG/telemetry
NXP	PF8100 / PF8200	PMIC rails (DS)	Multi-rail mgr	ADC + PG	Prog. tables	PG/IRQ	I²C	Logs (hosted)	—	Yes (variants)	i.MX/S32 ecosystem PMICs
NXP	MC33772C	Pack domain (DS)	High-channel ADC	ADC (cells V/I/T)	Prog. limits	INT	SPI/iso	Logs (hosted)	—	Yes	Battery-domain telemetry (HV side)
Renesas	ISL28022	Up to tens of V (DS)	kHz-class ADC	ADC (bus V/I)	Prog. limits	INT (family)	I²C	Counters	Low	—	General DC rail metering
Renesas	ISL68127	Controller domain (DS)	Multi-phase digital	ADC + PG/telemetry	Prog. tables	PG/INT	PMBus	Black-box support	—	—	Multi-phase w/ PG aggregation
onsemi	NCP308 / NCV308	Logic-level (DS)	Supervisor-fast	Window/Reset	Hysteresis options	RESET/PG	—	—	Very low	NCV = Yes	Simple reset/PG bricks
onsemi	NCS21871 / NCV21871	Op-amp range (DS)	Wide-BW op-amp	Kelvin front-end	—	—	—	—	Low	Yes (NCV)	Low-drift diff amp for remote sense
Microchip	PAC1934	Logic-level (DS)	kHz-class ADC (4ch)	ADC (V/I/Power/Energy)	Prog. limits	INT (family)	I²C/SMBus	Energy accumulator	Low	—	Great for multi-rail statistics
Microchip	MCP6C02	Up to ~65 (DS)	Sense amp, fast	Kelvin front-end	—	—	—	—	Low	—	Low-offset high-side sense
Microchip	MCP39F511A	Mains/AC domain	Energy-meter SoC	ADC (power)	Prog. limits	INT (host)	UART/SPI (family)	Energy logs	—	—	Input-side evidence (optional)
Melexis	MLX91220	Non-intrusive (Hall)	~DC–300 kHz (DS)	Peak capture (via comparator/ADC)	External	External	—	—	—	Yes (family)	Isolated current sensing for spikes

Notes: Numeric limits above are indicative; confirm exact ranges, bandwidth, and Iq in each device’s datasheet and select variants (e.g., -Q1/NCV) for automotive where needed.

Validation Checklist — Engineering Runlist

Validation checklist covering measurement matrix, threshold sweep, false-positive rate, timeline alignment, export, and A/B comparison — Run a complete, repeatable plan: matrix the operating points, sweep thresholds, align timestamps, export records, and compare A/B KPIs.

Quick-pass items

Measurement matrix: Load × Temp × Mode (PFM/PWM) × VIN.
Threshold sweep with upper/lower limits, hysteresis, and debounce window.
Timestamp alignment with PG/PLL and load steps for causality.
Record export: CSV / register dump / black-box counters.
A/B comparison: Vpp, RMS, event density, spectral peak location.

Load	VIN (Min/Typ/Max)	Temp (°C)	Mode	Metrics (Vpp/RMS/Events)	Notes
Light (<10%)	Min / Typ / Max	-40 / 25 / 85	PFM	—	PFM burst masking?
Mid (40–60%)	Min / Typ / Max	-40 / 25 / 85	PWM	—	Spectral peaks?
Heavy (>80%)	Min / Typ / Max	-40 / 25 / 85	PWM	—	Current-limit knee?
Dynamic steps	Min / Typ / Max	-40 / 25 / 85	PFM / PWM	—	ΔI, slew, duty sweep

Threshold sweep & false-positive rate

Sweep upper/lower limits while logging events/hour. Choose the tightest thresholds that keep FPR ≤ target (e.g., ≤0.5/h). Track P95/P99 to verify stability under temperature and mode changes.

Timeline alignment

Align PG/IRQ, PLL/clock, and load steps on a shared timestamp base. Store event_id, ts, and tags (VIN/Load/Mode/Temp) to explain causality during reviews.

Exit criteria: Vpp, RMS, and event density all improve (≥30% recommended), dominant spectral peak reduces/broadens, and percentile metrics (P95/P99) improve with no new false positives.

FAQs — Practical, Engineer-to-Engineer

Why do light-load PFM conditions often false-trip, and how should debounce/hysteresis be set?

PFM bursts create envelope peaks that exceed fixed peak thresholds without indicating a real fault. Use mode-aware tables: relax peak limits in PFM, keep RMS windowed. Add 2–5 ms debounce or N-in-window voting, and 10–30% hysteresis. Verify against your acceptable false-positive rate target under min/max VIN and temperature.

Peak-hold versus ADC sampling — which suits spike-dominant ground bounce?

Start with peak/envelope detection plus a fast comparator to catch rare spikes; add pulse stretching for IRQ visibility. Use ADC sampling for statistics (RMS, percentiles) and spectra. Keep anti-aliasing light enough to avoid masking resonances; log both channels on a common timeline for correlation.

Sense routing is coupled by the SW node — how do I wire and shield?

Route differential, short, and tight to the return path; avoid broadside passes near the SW node. Add shield only if the return is controlled and bonded at one point. Prefer spring-ground probe tips over long ground leads. Validate by A/B routing moves during dynamic-load tests.

Set thresholds high or low? How to define an “acceptable glitch”?

Use amplitude and duration: a peak limit for transients and a windowed RMS limit for continuous noise. Define an acceptable glitch as not violating functionality and staying within a bounded rate (events/hour). Sweep thresholds to achieve your target false-positive rate while preserving genuine events.

Can spectral peaks help locate layout issues?

Yes. Persistent peaks near LC corner or package/ESL resonances usually implicate loop area, via count, or component placement. Confirm by A/B moving decouplers, shortening returns, or adjusting compensation. Track peak frequency shifts and amplitude reduction after each change to prove causality.

How do I keep remote Kelvin sensing from disturbing loop stability?

Use a high-input-impedance differential amplifier; place RC only in the monitor branch, not on the control node. Keep leads short and symmetric; avoid routing across noisy planes. After adding the front-end, run a stability check (load step and phase margin) to confirm poles are unchanged.

How should thresholds and delays change during automotive crank?

Apply a startup/crank mask window; widen undervoltage hysteresis and relax temporary thresholds only within that window. Keep a fast over-voltage path for load-dump. Log every action with VIN and temperature, and return to nominal limits automatically after the recovery timer expires.

How do multi-rail PG logics avoid “false interlock” shutdowns?

Normalize PG pulse width, add de-glitch time, and aggregate with AND or majority vote depending on criticality. Decouple upstream alerts from downstream resets using hold-off and retry throttling. Align events to a shared tick so supervision firmware can infer the true initiator.

What does spread-spectrum do to monitoring and measurement?

It disperses energy, lowering narrow peaks but raising the noise floor slightly. Use longer statistical windows and peak detectors with adequate hold to avoid under-reporting. When comparing A/B, keep spread-spectrum states identical; otherwise peak metrics are not directly comparable.

How to compute event density and use P95/P99 as regression KPIs?

Use fixed windows (e.g., 1 minute) to count events and compute Vpp/RMS distributions. Tag with VIN, load, mode, and temperature so daily baselines are comparable. Track P95/P99 and events/hour before and after fixes; require sustained improvement across conditions, not just a single run.

When do I need isolation and backfeed protection?

Use isolation on cross-domain or long-cable links and whenever automotive, hot-plug, or ESD/Surge exposure exists. Add UVLO and backfeed protection so the monitor never powers sensitive domains inadvertently. Verify propagation delays still meet your event alignment needs.

How do I choose ADC sampling rate and anti-alias filtering?

Set the passband to cover at least 2–5× the highest problem frequency; choose sampling rates accordingly. Keep anti-alias RC mild to avoid hiding resonances; supplement with peak detection for rare spikes. Validate by injecting known tones and cross-checking spectrum shifts after fixes.

When is a window comparator enough, and when do I need bus + logs?

If you only need hard protection and simple PG/RESET, a window comparator with hysteresis is sufficient. If you must prove trends, correlate events, or debug intermittents, add bus telemetry and black-box logs. Consider both: comparator for fast cutout, ADC+bus for evidence.

Current-limit knee causes false spikes — what helps?

Reduce step amplitude or slew, add local bulk capacitance, and tune compensation/AVP for faster but controlled recovery. Use peak-hold plus debounce to avoid single-shot trips. Verify improvement by lower spike counts and reduced Vpp during heavy-load transitions.

Soft-start coupling triggers alerts — how should I handle it?

Apply a startup mask window that suppresses alerts until the rail settles. Use a separate set of startup thresholds and a minimum hold-off before normal monitoring resumes. Log the transition so audits show the system behaved by design during initialization.

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