Power Management ICs (PMIC): LDO, DC-DC, Protection, Supervisors

What is a PMIC? — System-level power coordinator

A PMIC coordinates multiple rails—conversion, protection, supervision and sequencing—so a board powers up cleanly and safely.

Voltage regulation
Battery management
Sequencing
Thermal
Power path

Multi-rail PMIC map: input battery/adapter with eFuse/ideal-diode protection feeding a PMIC; three rails buck→CPU, LDO→sensor/ADC, buck-boost→RF/IO; PG/RESET and sequencing arrows — Fig.A — Multi-rail power map (input → protection → PMIC → buck/LDO/buck-boost rails with PG/RESET & sequencing).

What a PMIC does

Conversion: buck / boost / buck-boost / LDO to generate stable rails.
Protection: eFuse, load-switch, ideal-diode / ORing, surge control.
Supervision: voltage supervisors, reset & watchdog for brownout immunity.
References: low-noise/low-drift V_ref for ADC/DAC & sensors.
Sequencing & power path: PG chains, tracking, USB-PD source/sink.

Boundaries & common confusions

PMIC vs single regulator: PMIC handles multi-rail coordination & protection.
PMIC vs Battery-management IC: BMS manages charge/fuel-gauge; PMIC manages board-level rails.
When a PMIC isn’t needed: single rail, low power, no strict sequencing → single LDO/buck may suffice.

Takeaway: PMIC is the board’s power coordinator—it enforces order, safety and predictability across multiple rails, rather than being “just one regulator.”

LDO vs Buck/Boost — When to choose which

Efficiency/thermal and noise/transient pull in different directions. Use this quick math + decision map to make a safe first pick. For quiet rails choose LDO; for heavy loads or big voltage gaps, choose buck/boost; combine buck→LDO for “efficient yet quiet”.

Efficiency/thermal and noise/transient pull in different directions...

Deep dive: What is an LDO? Definition, dropout, and 5-step selection →

LDO thermal loss

P_loss = (V_IN − V_OUT) × I_OUT

Buck effective loss

P_loss ≈ (1 − η) × V_IN × I_OUT

LDO minimum input

V_IN,min = V_OUT + V_DROPOUT

Rule-of-thumb thresholds

If P_loss(LDO) ≳ 0.5–1.0 W or expected efficiency < 70–80% → pick a buck.
If I_OUT ≲ 50–150 mA and rail is noise-sensitive → pick an LDO.
For “efficient yet quiet”, use buck → LDO (front-end buck feeds a low-noise LDO).

Noise & transient checklist

Ripple/Noise: LDO is quiet; buck needs proper LC and layout.
PSRR: LDO wins at mid-high frequencies; buck injects switching ripple.
Load-step: Buck requires compensation & loop bandwidth; LDO depends on C_OUT & ESR range.

Decision map for LDO vs buck by heat/efficiency, noise and load current; sweet spot shows buck feeding LDO for efficient yet quiet rails — Fig.B — LDO ↔ Buck decision map (heat/efficiency • noise • load current). The “buck→LDO” area yields quiet rails with high efficiency.

Minimal chain — MCU sensor rail (quiet first)

VIN 5V → LDO 3.3V → Sensor/ADC · Pick a low-noise LDO, check PSRR @100k–1 MHz, place decoupling close to loads.

Minimal chain — Wireless rail (efficiency first)

VIN 5V/USB → Buck 3.3V → RF/IO · Control EMI via loop area & grounding; add a 50–100 mA LDO post-filter if the RF is sensitive.

Unsure after quick math? Send your rail map — 48h, 3 safe options

Power Protection ICs — eFuse / Load-Switch / Ideal-Diode / Surge

Ports and inputs fail for the same costly reasons: short, reverse, surge and uncontrolled inrush or backfeed. Protection ICs add controlled limits, timing and directionality that MOSFET-only tricks can’t guarantee.

Quick decision table

Scenario / Need	Required capability	Recommended IC	Placement	Key params / notes
On/off with soft-start; quick discharge	Controlled slew, output discharge	Load-Switch IC	Branch / peripheral rail	R_DS(on), optional I_LIM, QOD, slew
OCP/OVP, short-circuit limit, thermal foldback, backfeed block	Current/voltage thresholds, fault latch/auto-retry	eFuse / Hot-Swap IC	Input / port front	I_LIM, OVP/UVP, TSD, latch, ideal-diode option
Dual-source ORing; reverse-current blocking	One-way conduction, fast switchover	Ideal-Diode / ORing Ctrl	Source merge node	Reverse threshold, turn-off time, drop
Automotive/industrial surge & load-dump	Over-voltage clamp/foldback, energy handling	Surge-Stopper IC	Very front of input	Transient/steady OVP, current limit, SOA, ISO7637

Inrush quick math

I_inrush ≈ C_load · ΔV / T_ramp

Soft-start in load-switch/eFuse increases T_ramp. Large capacitive loads without QOD can retain charge and cause overshoot at re-plug. Always size against the source/port limit (USB, adapter, battery).

When QOD is necessary

Capacitive loads & hot-plug ports (USB/Type-C).
Multiple branches sharing a mid-bus—avoid residual voltage back-bias.
Sequenced rails that must return to a known 0 V before restart.

Protection placement & timing: input surge-stopper/eFuse, branch load-switch, USB port eFuse + ideal-diode feeding power-path; faults interact with EN and PG timing — Fig.C — Protection placement and timing across input, branches and USB port; protection acts before PG/RESET.

Three high-stakes rules:

USB ports: always eFuse (limit + QOD) and reverse-block (ideal-diode). Verify I_inrush.
12 V automotive: front-end surge-stopper/hot-swap before efficiency tuning.
Dual sources: ideal-diode/ORing is mandatory to avoid backfeed and bus dips.

Supervisors & Reset — Brownout Immunity

Random reboots usually stem from rail timing and brownout issues. Pick the right monitor (threshold vs window), set delays/hysteresis, and keep PG/RESET away from switching noise. Add a watchdog where software can stall.

Monitor types

Threshold: single limit + fixed delay; simple and cheap.
Window: upper & lower bounds; more robust in noisy/multi-rail systems.
Watchdog: independent timer to recover stalled software.

Selection checklist

Threshold accuracy & temperature drift.
Delay range & reset polarity / open-drain.
Minimum pulse width and noise filtering.

Start-up and power-down timing windows with PG daisy chain, sequencer controlling EN, and reset release after rails settle — Fig.D — Start-up/shutdown timing windows; PG daisy chain feeds sequencer EN; release reset after rails settle.

Suggested thresholds & delays

Rail	Typical threshold	Delay suggestion	Notes
3.3 V digital	2.9–3.1 V window	Power-up 50–200 ms / Power-down 5–20 ms	Ignore short dips; prevent nuisance resets.
1.2–1.8 V core	90–95% of V_nom	20–100 ms	Match CPU/DDR timing; respect min hold time.
Sensors / analog	95–98% of V_nom	100–300 ms	Stabilize analog first; then enable interfaces.

Safe timing templates

CPU → DDR → IO: PG daisy chain + fixed delays; shutdown in reverse order.
RF → Baseband → Peripherals: bring RF last, drop first to avoid spurs.
USB-PD → Core → High-current peripherals: negotiate PD first, then core, then heavy loads.

Validation essentials

Capture PG/RESET edges and pulse width.
Check threshold stability under load steps.
Watchdog timeout policy aligned with software recovery.

Routing rules

Keep PG/RESET and EN away from switch nodes and noisy returns.
Place dividers near the sensed rail; short, same-layer route.
Add RC filtering for remote sense to avoid spike triggers.

Voltage References — Series vs Shunt

For most MCU/SAR-ADC rails, Series references are the safe default. Use Shunt references when wide input range, external clamping or multi-node sharing helps. For ≥20-bit ΔΣ systems, favor low noise/low drift refs with a proper buffer and thermal control.

Series vs Shunt — quick comparison

Dimension	Series Reference	Shunt Reference
Operation	Acts like a regulated source; needs supply headroom.	Acts like a precision clamp; sets V by current through a resistor.
Noise (0.1–10 Hz / wideband)	Often lower wideband noise; stable with specified C/ESR.	Low 0.1–10 Hz parts exist, but layout & bias matter more.
Tempco / long-term drift	Low ppm/°C options; good long-term drift families.	Widely varies; pay attention to bias current over temp.
Load drive / buffering	Limited drive; buffer for heavy/fast-changing loads.	Almost always buffer for stability and line isolation.
Input range / special uses	Needs V_IN > V_ref + headroom.	Wide range; useful for clamps & shared mid-nodes.
Cost / power	Efficient at steady bias; fewer passives.	Resistor current wastes power; flexible but cost in bias.

Noise reading & quick math

Check nV/√Hz and 0.1–10 Hz noise. For a rough wideband estimate:

V_n,rms ≈ e_n × √BW

For 16-bit SAR, BW is typically tens of kHz. Keep V_n,rms ≲ LSB/2 including ADC front-end filtering.

Drift budgeting

Budget ppm/°C × ΔT along with initial accuracy and long-term drift. A thermally tight layout (short Kelvin sense) reduces gradients; re-calibrate for high-accuracy systems.

When to add a buffer

Multiple ADC channels or large sampling capacitor.
DAC load varies with code or external circuitry.
Remote reference routing; need isolation and stability.

Buffer amplifier picks

Low noise, low bias, rail-to-rail I/O if needed.
Stable with capacitive loads; add small series R + C low-pass.
Use a star-point ground; Kelvin sense the reference node.

Series vs Shunt reference concept: series as regulated source with headroom; shunt as precision clamp with bias resistor; buffer and RC filter driving ADC/DAC — Fig.E — Series vs Shunt concepts and a typical buffered Vref feed for ADC/DAC.

Practical thresholds:

16-bit SAR “good enough”: 0.1–10 Hz noise ≤ 1–3 µV_pp; integrated wideband noise ≲ LSB/2; tempco ≤ 10–20 ppm/°C.
24-bit ΔΣ: prioritize low 0.1–10 Hz noise and long-term drift; always buffer + RC filter; allow warm-up and periodic calibration.

Power Sequencing & Tracking

Multi-rail boards fail when order, hold time or residual charge is overlooked. Use proven tracking modes, PG daisy chains and soft-start to shape safe ramps; handle pre-bias and dual sources with ideal-diode/ORing.

Tracking modes — when to use which

Mode	Benefits	Risks	Typical use
Coincident	Same slope, rails arrive together; simple coordination.	Cross-coupling can bite if one rail lags or droops.	Core + IO together; some analog domains.
Ratiometric	Maintains voltage ratios; gentle for interfaces.	Needs careful ramp control and sensing.	Mixed-signal ADC/DAC, sensor interfaces.
Offset	Enforced order and hold times; robust with PG gating.	Longer start-up; tune delays to avoid brown-in.	CPU → DDR → IO; RF → Baseband → Peripherals.

Three-rail templates: Offset (CPU→DDR→IO), Coincident and Ratiometric with PG, EN, soft-start, pre-bias handling and reverse-order shutdown — Fig.F — Three-rail templates with PG daisy chain, soft-start, pre-bias and reverse-order shutdown.

PG daisy chain & gating

Upstream PG gates downstream EN; add de-glitch & min high-time.
Release reset only after all required rails are within window.
Mirror PG to a monitor pin for validation captures.

Soft-start, pre-bias & ORing

Program T_rise to limit I_inrush; coordinate across rails.
Ensure buck supports pre-bias start or add ideal-diode to prevent reverse conduction.
Use ideal-diode/ORing for dual sources; integrate fault signals into timing.

“Replacement switches” — practical swaps

Buck ↔ LDO: keep PG/EN timing & T_rise; verify downstream remains unchanged.
Single-source → Dual-source: insert ideal-diode/ORing; include its PG/fault into the chain.
Load-switch → eFuse: preserve EN logic; re-size I_LIM/QOD; re-check inrush.

Bring-up validation

Capture PG/EN/RESET ordering at start-up and power-down.
Measure T_rise, I_inrush and minimum hold times.
Brown-in/out and hot-plug behavior under worst loads.

Common pitfalls

PG glitches used directly as EN without filtering.
Pre-bias ignored, causing reverse conduction at start-up.
Dual-source ORing without integrating fault/PG into timing.

Share your 3-rail sketch — 48h, validated sequencing/tracking plan

USB-PD & Power Path (Type-C)

Ports fail for the same reasons: backfeed, hot-plug surges, wrong roles, or over-current on non-eMarker cables. ≤5V/3A: Type-C is fine with proper port protection (eFuse + reverse block). 20V/5A: USB-PD negotiation + 5A eMarker cable + power-path control are mandatory.

Roles & capabilities — quick reference

Role	CC detect (Rp/Rd)	BC1.2	USB-PD (PDO/Swap)	VCONN / eMarker	Power-Path focus	Protection focus
Source	Advertise via Rp	Charge profile @5V	Offer PDOs; PR/DR swap	May supply VCONN; must gate 5A only with eMarker	VBUS sourcing, current limit, thermal	eFuse + ideal-diode (reverse block), TVS as needed
Sink	Detect via Rd	Identify legacy sources @5V	Request PDOs; PR/DR swap	Check cable current capability	VBUS sinking, inrush control, dead-battery	eFuse (inrush/short), reverse block to mid-bus
DRP (dual-role)	Dynamically swap Rp/Rd	Legacy fallback when no PD	PR/DR swaps, role policy	VCONN control for cable ID	Bidirectional power-path with prioritization	Symmetric protection in both directions

BC1.2 vs USB-PD — when to use

BC1.2: 5V legacy charging profiles (≈0.5–1.5A). No 9/15/20V negotiation.
USB-PD: Negotiates PDOs (5/9/15/20V…) and current; enables DRP, role/data swaps.
Above 3A@5V or any voltage >5V → use PD and validate cable capability.

Power-Path controller — key duties

Path management: source/sink switching, priority, merge.
Protection: cooperate with eFuse/ideal-diode (OV/OC, reverse block, thermal foldback).
Dead-battery mode; VCONN supply for eMarker; FAULT/PG/INT reporting.

Cable & eMarker: ≤3A: non-eMarker cable allowed. >3A up to 5A: 5A eMarker cable required. Source must gate 5A only when cable advertises 5A; Sink must still limit current and manage heat.

Port protection essentials

eFuse for current limit + inrush (QOD recommended);
Ideal-diode or reverse-blocking path to prevent backfeed;
ESD on CC/VCONN, selective TVS on VBUS; short, low-impedance returns;
Coordinate FAULT with PD/power-path logic to avoid re-strike.

Layout & validation highlights

Compute inrush; tune soft-start vs source capability.
Measure PDO transitions, PR/DR swaps, and temperature rise at worst case.
Check non-eMarker cable behavior (limit current) and reverse insertion.

USB-C port with eFuse current limit and ideal-diode reverse block feeding a PD power-path controller; VCONN to eMarker; protection before PG/EN timing — Fig.G — Type-C/USB-PD power path with eFuse and ideal-diode protection feeding a power-path controller; VCONN/eMarker shown.

Minimal compliant chains — 5V/3A and 20V/5A

Profile	Protocol	Cable requirement	Controller blocks	Protection blocks	Validation focus
5V / 3A	BC1.2 or PD @5V (fixed PDO)	Non-eMarker OK	Type-C CC detect, optional PD, simple power-path	eFuse (inrush/OC) + ideal-diode reverse block; ESD/TVS as needed	I_inrush, steady-state temp, unplug/re-plug behavior
20V / 5A	USB-PD with negotiated PDOs; PR/DR swap as policy	5A eMarker cable required	PD controller + bidirectional power-path; VCONN supply	High-current eFuse (QOD) + ideal-diode; robust thermal & surge handling	PDO transition transients, 5A thermal budget, role swaps, fault timing

Tip: Validate PD logs (PDOs, PR/DR swaps), then correlate with oscilloscope captures of VBUS ramp, inrush and port thermals at worst-case.

Not sure about cable/role/limits? Share your port diagram — 48h, 2 minimal compliant chains

Quick Shortlist — Cross-brand picks

A practical “3 picks per category” to move from selection to quoting. Each table lists a conservative, a performance and a rugged/AEC-Q option. Replace the placeholder PNs with your in-stock parts before publishing.

LDO Regulators

3 picks

Slot	PN / Brand	VIN / VOUT	I_OUT	Package	Highlights	AEC-Q
Conservative	TI-LDO-X1 / TI	2.7–6 V → 3.3 V	300 mA	SOT-223 / SOT-23	Low-Iq, stable ESR window	N
Performance	ST-LDO-UQ / ST	1.8–5.5 V → 1.8 V	500 mA	DFN/QFN	Ultra-low noise, high PSRR	N
Rugged / AEC-Q	REN-LDO-AQ / Renesas	3–40 V → 5 V	150 mA	SOIC / HTSSOP	Wide VIN, thermal, watchdog option	Y

Tip: Analog rails first—low noise & PSRR; ensure dropout headroom.

V_DROPOUT margin
Output cap ESR window
RθJA thermal budget

Buck Converters

3 picks

Slot	PN / Brand	VIN / VOUT	I_OUT	Package	Highlights	AEC-Q
Conservative	NXP-BUCK-S1 / NXP	4–24 V → 5 V	2 A	SOIC / TSSOP	Wide VIN, easy compensation	N
Performance	TI-BUCK-UQ / TI	2.9–17 V → 3.3 V	3 A	QFN micro	High η, spread-spectrum EMI	N
Rugged / AEC-Q	ON-NCP-AQ / onsemi	6–40 V → 5/3.3 V	2 A	SOIC / DFN	Automotive transients, hiccup OC	Y

Tip: High current or big ΔV → buck; validate compensation & EMI early.

Loop compensation
Switch loop area
Hot-spot thermal

Boost / Buck-Boost

3 picks

Slot	PN / Brand	VIN / VOUT	I_OUT	Package	Highlights	AEC-Q
Conservative	MCH-BST-S1 / Microchip	1.8–5 V → 5/12 V	0.6 A @5 V	MSOP / DFN	Simple start-up, internal switch	N
Performance	TI-BB-UQ / TI	2–18 V → 3.3–12 V	2 A (buck-boost)	QFN	Seamless mode, high η	N
Rugged / AEC-Q	ON-BST-AQ / onsemi	3–36 V → 12 V	1 A	SOIC / DFN	Cold-crank, load dump tolerant	Y

Tip: Battery→5/12 V rails; ensure start-up under load.

Cold start/UVLO
Peak current limits
Sync vs diode topology

Protection (eFuse / Load-Switch / Ideal-Diode / Surge)

3 picks

Slot	PN / Brand	VIN	I_LIM / I_PATH	Package	Highlights	AEC-Q
Conservative	MCH-LSW-S1 / Microchip (Load-Switch)	1.8–5.5 V	1–2 A	SOT / DFN	Soft-start, QOD	N
Performance	TI-EFUSE-UQ / TI (eFuse)	2.7–18 V	2–3 A	QFN	OCP/OVP, latch/auto-retry, rev-block	N
Rugged / AEC-Q	REN-ID-AQ / Renesas (Ideal-Diode/ORing)	4–36 V	3–5 A path	SOIC / DFN	Fast reverse block, surge-ready	Y

Tip: Port/input first—eFuse + reverse block; compute inrush.

I_LIM & QOD
Reverse current block
ISO/USB compliance

Voltage Supervisors / Reset

3 picks

Slot	PN / Brand	Threshold	Delay / Features	Package	Highlights	AEC-Q
Conservative	MCH-SV-S1 / Microchip	3.0 V (±1.5%)	140 ms; push-pull	SOT-23	Simple, robust	N
Performance	TI-SV-WIN / TI	Window (±2%)	Adjustable, WDT	QFN	Noise-immune, watchdog	N
Rugged / AEC-Q	REN-SV-AQ / Renesas	Configurable window	Long delay, open-drain	TSSOP	Brownout immunity	Y

Tip: Window + delay to avoid nuisance resets.

Threshold accuracy & drift
Delay range
Reset polarity

Voltage References

3 picks

Slot	PN / Brand	Vref	Noise / Tempco	Package	Highlights	AEC-Q
Conservative	ST-REF-S1 / ST (Series)	3.0 V	Low / 20 ppm/°C	SOT-23	Stable with C, easy drive	N
Performance	TI-REF-UQ / TI (Series)	2.5 V	Ultra-low / 10 ppm/°C	QFN	Low 0.1–10 Hz noise	N
Rugged / AEC-Q	REN-REF-AQ / Renesas (Shunt)	2.5 V	Low / 15 ppm/°C	SOIC	Clamp use, wide bias	Y

Tip: Series for most SAR; buffer for ΔΣ & multi-load.

0.1–10 Hz noise
ppm/°C drift
Buffer stability

Sequencers / Trackers

3 picks

Slot	PN / Brand	Rails / Mode	Controls	Package	Highlights	AEC-Q
Conservative	TI-SEQ-S1 / TI	2–4 rails / Offset	PG chain, fixed delays	TSSOP	Simple, robust timing	N
Performance	ST-TRK-UQ / ST	3–6 rails / Coincident, Ratio	Programmable ramps	QFN	Smooth tracking	N
Rugged / AEC-Q	ON-SEQ-AQ / onsemi	2–4 rails / Offset	Fault gating, reset	SOIC	Automotive timing	Y

Tip: Pick template: Offset / Coincident / Ratiometric.

PG de-glitch
T_rise alignment
Reverse-order shutdown

USB-PD / Power-Path

3 picks

Slot	PN / Brand	Role / Voltage	Path current	Package	Highlights	AEC-Q
Conservative	MCH-USBC-S1 / Microchip	Sink 5/9 V (PD)	3 A	QFN	Dead-battery, simple path	N
Performance	TI-USBC-DRP / TI	DRP 5–20 V (PD)	5 A path	QFN	PR/DR swaps, VCONN/eMarker	N
Rugged / AEC-Q	ON-USBC-AQ / onsemi	Source 5–20 V (PD)	5 A path	QFN / SOIC	Reverse block + eFuse coop	Y

Tip: 20V/5A needs PD + 5A eMarker + reverse block.

PDO logs
I_inrush & thermals
Cable capability

Specs vary by sub-variant — verify latest datasheet before build. Submit your BOM — 48h, 3 safe cross-brand options

Troubleshooting — Problem → Cause → Verify → One-shot Fix

Match the symptom → capture proof under “Verify” → apply the “One-shot Fix”. Always verify first before changing hardware/firmware. Related topics to link later: Protection / Supervisor / Buck / Sequencer.

Power-up oscillation / repeated start attempts

Common

Problem	Likely causes	Verify (scope)	One-shot fix
VOUT rises then collapses in cycles	Soft-start too fast → I_inrush exceeds source; unstable compensation; output cap ESR outside stable region; pre-bias not handled	CH1=VOUT, CH2=IOUT, CH3=EN/PG; trigger on VOUT falling edge (repeating); watch current-limit/thermal foldback	Lengthen soft-start / lower current limit; correct compensation & ESR; enable pre-bias start or add ideal-diode ahead

→ Link later: Buck / Protection / Sequencer

Brownout (voltage dip causes reset)

Supervision

Problem	Likely causes	Verify (scope)	One-shot fix
Reset after load step / supply dip	Supervisor thresholds/delays too tight; PG directly drives EN without de-glitch; main rail sags (trace resistance/ground return)	CH1=VCORE, CH2=3V3, CH3=RESET, CH4=PG; trigger on RESET falling edge; measure dip depth & duration	Use windowed supervisor and relax delay; PG → Sequencer → EN daisy chain; add local decoupling & improve ground return

→ Link later: Supervisor / Sequencer

Overshoot (power-up / unload exceeds spec)

Loop/Layout

Problem	Likely causes	Verify (scope)	One-shot fix
VOUT exceeds upper tolerance	Excess loop bandwidth/underdamped; rapid unload; synchronous rectifier back-feed; noisy FB/Kelvin routing	Trigger when VOUT > limit; log amplitude & duration; compare with BW limit ON/OFF	Retune compensation; add slight ESR/RC; small RC snubber at load; clean FB/Kelvin routing

→ Link later: Buck

Port current-limit false trip (drops right on plug-in)

Type-C/PD

Problem	Likely causes	Verify (scope)	One-shot fix
Power cuts immediately at plug-in	I_inrush not limited; too-narrow detection window; 5A allowed without 5A eMarker; reverse current transient flagged as fault	CH1=VBUS, CH2=IOUT/Rsense, CH3=FAULT, CH4=CC/VCONN; trigger on FAULT falling edge; check slope & peak	eFuse soft-start + QOD; de-glitch current limit; allow 5A only with 5A eMarker cable; ideal-diode for reverse-block

→ Link later: Protection / USB-PD & Power-Path

Load-Dump / automotive surge damage

Automotive

Problem	Likely causes	Verify (scope)	One-shot fix
Parts fail or power loss after surge	No surge-stopper/hot-swap; TVS energy too low; SOA exceeded	Surge generator or equivalent; CH1=VIN, CH2=VOUT, CH3=IIN, CH4=FAULT; trigger when VIN > threshold; log SOA & thermals	Add surge-stopper (clamp/foldback); higher-energy TVS; derate & recheck thermal and return paths

→ Link later: Protection

Oscilloscope trigger presets

Power-up oscillation: Edge (fall) @ VOUT = 0.9·V_nom, holdoff 2–5 ms, BW limit ON, ≥100 MS/s.
Brownout: Pulse-width (low) on VCORE @ 0.9·V_nom, width > 50 µs; qualify with RESET.
Overshoot: Runt (positive) on VOUT, upper=1.05·V_nom, lower=V_nom, time > 10 µs.
Port limit false trip: Edge (fall) on FAULT + math/DB for IOUT peak; add CC/VCONN digital trigger.
Load-Dump: Edge (rise) on VIN > 1.3×rated; 1–10 ms/div; optional thermal camera sync.

PG/RESET verification — minimal closed loop

Wiring: CH1=PG, CH2=EN, CH3=RESET, CH4=critical VOUT; common ground point.
Startup capture: Record full power-up; check PG → EN → RESET order & pulse widths.
Window check: Confirm supervisor threshold (%V_nom) and delay (ms) are within recommended range.
Power-down: Cut upstream source; verify reverse-order shutdown & minimum hold time.
Disturbances: Apply load steps / hot-plug; watch for false trips.
Conclusion: Log “evidence (waveforms) → chosen fix”, then rerun to confirm.

FAQ — Engineering & Selection

What does a power management IC do?

At board level, a PMIC coordinates multiple rails: regulation (buck/boost/LDO), protection (eFuse/load-switch/ideal-diode), supervision/reset, and sequencing. It turns a battery or adapter into stable rails with predictable startup/shutdown, while controlling inrush, limiting heat, and preventing brownouts that crash CPUs or radios.

→ See: What is a PMIC

What is a power management IC?

A power management IC (PMIC) integrates several power functions—converters, references, protection, and power-path control—into one device or tightly coupled set. Compared with many discrete parts, it reduces area, routing complexity, and timing risk, especially on dense multi-rail systems where sequencing and brownout immunity matter.

→ See: What is a PMIC

What is the IC in a power supply?

In modern designs, “power-supply IC” usually means a switching regulator (buck/boost) or an LDO that sets a regulated rail. Around it, PMICs add supervisors, references, and protection ICs to meet timing, noise, and safety targets—ensuring rails start cleanly and survive faults or hot-plug events.

→ See: LDO vs Buck/Boost

What type of IC is used in voltage regulation?

For higher currents or large VIN–VOUT gaps, buck/boost converters deliver efficiency. For low current or ultra-low-noise rails, LDO regulators shine. Many PMICs cascade both: a high-efficiency buck feeding quiet LDO rails for ADCs, clocks, or radios, balancing ripple, PSRR, thermal budget, and BOM.

→ See: LDO vs Buck/Boost

How to test a power IC?

Probe VIN, VOUT, and PG/RESET. Verify startup ramp, load-step recovery, ripple, and dropout. For protection parts, measure current-limit, short-circuit response, and inrush using C·ΔV/Tr. Use a short coax ground, enable bandwidth limit, and capture brownout or fault-latch behavior for repeatability and evidence.

→ See: Troubleshooting , Power protection

How to know if power IC is damaged?

Red flags include abnormal quiescent current, VOUT stuck low/high, persistent thermal shutdown, or PG never asserting. Check for output shorts and isolate loads. If the IC overheats unloaded or fails soft-start repeatedly, replace it, then review ratings, compensation, layout, and heat spreading around the package.

→ See: Troubleshooting

Can power IC be replaced?

Yes—start with pin-compatible families. If not, match control behavior (EN/PG logic), compensation, soft-start profile, OCP/OVP thresholds, and thermal pad footprint. Re-validate sequencing with other rails and confirm brownout immunity and inrush limits before committing the alternate to EVT/DVT builds or field repairs.

→ See: Quick shortlist (CTA: Submit your BOM)

How to check if the power supply is faulty?

Load the input and watch droop, verify loop stability (no oscillation on steps), and check sequence order relative to CPU/DDR rails. Brownouts or bouncing during inrush indicate soft-start, eFuse/load-switch, or PG thresholds need tuning. Capture waveforms and correlate with FAULT/RESET pins for root cause.

→ See: Troubleshooting , Power sequencing/tracking , Power protection

What is IC regulated power supply?

It’s a power stage built around integrated regulators—buck/boost or LDO—to keep a rail within tolerance across load and VIN variation. Compared with linear transformer bricks, IC-based supplies enable compact multi-rail boards with sequencing, supervision, and protection to meet thermal and reliability goals.

→ See: What is a PMIC , LDO vs Buck/Boost

What is IC voltage?

In PMIC context, it means allowable VIN/VOUT ranges and internal reference levels. Check absolute maximums, dropout and headroom for LDOs, and duty-cycle/ton limits for converters. Ensure margins across tolerance and temperature, and verify PG thresholds align with your rails’ safe operating windows.

→ See: LDO vs Buck/Boost

What does power management do?

Power management balances efficiency, noise, and timing. It sequences rails, protects ports and batteries, enforces current/voltage limits, and keeps thermals within budget. A well-planned PMIC architecture reduces field failures, simplifies second-sourcing, and provides predictable startup/shutdown even under hot-plug or brownout stress.

→ See: What is a PMIC , Sequencing

How to use IC in a circuit (for power rails)?

Start from loads: voltage, current, noise, and transients. Choose buck/boost/LDO accordingly, then add input protection (eFuse/ideal-diode) and supervisors for critical rails. Keep switch loops tight, place input/output capacitors close, separate PG/EN from noisy nodes, and validate sequencing templates against CPU/DDR needs.

→ See: LDO vs Buck/Boost , Power protection , Sequencers/trackers

Which IC is the best?

There’s no universal “best.” Quiet analog rails favor low-noise LDOs; heavy loads demand buck/boost; harsh inputs need eFuses or surge-stoppers. Build a cross-brand shortlist (3 parts), then verify timing, inrush, thermals, and protection behavior on your board before freezing the choice for production.

→ See: Quick shortlist

What devices use IC? (PMIC examples)

Phones, wearables, and IoT nodes rely on PMICs for size, battery life, and multi-rail coordination. Automotive ECUs add surge and reverse protection. USB-C hosts/sinks use PD and power-path controllers with eFuses and ideal-diodes to negotiate PDOs cleanly and pass compliance and thermal checks.

→ See: USB-PD & power-path , Power protection ICs