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Which ADC IC Should I Pick? (Small-Batch Selection Guide)

September 15 2025
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Small-batch guide to choosing an ADC IC: set resolution, sampling rate/bandwidth, input type, interface, power and package; see scenario-based directions and request 3 safe options in 48h.

How to shortlist an ADC IC — two quick steps

Step 1 — Signal domain (bandwidth / sampling, input type & range)

≤ 200 kS/s, high precision/low noise → ΔΣ

ΔΣ trades bandwidth for higher effective resolution (ENOB) via oversampling and noise shaping—great for slow, precise measurements.

Small-batch tip: verify clean Vref/ground; even slow sensors still need anti-alias filtering.

Read more → Types
1–10 MS/s, general control/DAQ, low latency → SAR

SAR balances MS/s speed, resolution, latency, and power with simple peripherals—usually the easiest to bring up.

Tip: prefer differential inputs with proper driver/RC to improve immunity and linearity.

Read more → Types
> 20–40 MS/s, transients/imaging/IF sampling → Pipeline / Flash

High-speed use cases need Pipeline/Flash for throughput and front-end linearity—clock jitter and synchronization become critical.

Tip: expect LVDS/JESD204 links; plan routing and decoupling early.

Read more → Types

Thresholds are practical ranges. If you’re on the border, choose by latency/synchronization first, then verify power and interface feasibility.

Input type & range — Single-ended vs Differential; mV-level vs ±V domain

Differential inputs plus a sensible full-scale range improve common-mode rejection and usable dynamic range. For mV-level signals, prioritize front-end gain and a clean reference.

Read more → Front-End & Vref

Step 2 — System domain (interface, channels, package/rails/temp)

Interface: SPI (low pins, simple)

Great for 1–2 channels and moderate throughput; easy firmware. Bottlenecks appear as fs × bits × channels increases.

Read more → Interfaces
Interface: LVDS (parallel diff, mid-to-high speed)

Multiple differential pairs scale bandwidth with good immunity; mind timing, skew, and length matching.

Read more → Interfaces
Interface: JESD204 (high-speed serial, scalable)

Clean way to move very high data rates and keep channels in sync; clocking and link bring-up need discipline.

Read more → Interfaces

Throughput quick check ≈ fs × bits × channels / efficiency (rule-of-thumb only; see Interfaces for details).

Channels: Single

Simplest layout and firmware for control and single-point measurements.

Read more → Types
Channels: Dual (may need simultaneous sampling)

For phase/compare tasks, use simultaneous-sampling or alignable apertures; multiplexed SAR can work with careful timing.

Read more → Types
Channels: Multi (synchronized)

Arrays and multi-axis work demand phase consistency; prefer synchronized architectures and links.

Read more → Types
Package / environment / rails — QFN·SSOP·BGA, Industrial·AEC-Q, 1.8V·3.3V·5V

Package and temperature grade drive manufacturability and reliability; supply rails shape driver choices and power budget.

Read more → Supply & risk policy

Key Parameters to Decide Before Shortlisting

Resolution (ENOB)

Nominal bits rarely equal effective bits. Start from the smallest change you must resolve, convert it to %FS, and map to an ENOB target. Pick one to two bits of headroom and ensure reference noise stays well below ½ LSB(rms), otherwise resolution is wasted. Calibrate only after the front-end is quiet.

Read more → Resolution
Sampling Rate / Bandwidth

Don’t confuse the ADC’s fs with signal bandwidth. Budget a Nyquist guard (typically 20–30%) and set the anti-alias filter so out-of-band energy doesn’t fold back. Slow sensors still alias when switching noise leaks in. Decide by usable bandwidth, not a marketing max-rate.

Read more → Anti-alias
Input Type & Range

Single-ended is simple; differential buys common-mode rejection and dynamic range. Choose full-scale range so codes are used efficiently. mV-level inputs usually need gain and a low-impedance driver; high source impedance calls for buffering. Match FSR and Vref to the real signal.

Read more → Front-End & Vref
Interface Throughput

Quick check: throughput ≈ fs × bits × channels / efficiency. SPI is easy but hits limits early; LVDS adds lanes and immunity; JESD204 scales cleanly at very high rates with stricter clocking. Confirm framing overhead and firmware/FPGA resources before locking in.

Read more → Interfaces
Latency / Pipeline Delay

Control loops, protection trips, and synchronized arrays care about group delay. SAR is low-latency; delta-sigma adds filtering delay; pipeline/flash can add cycles. Decide by loop stability and channel-alignment needs, then shortlist devices within that architecture class.

Read more → Types
Noise / SNR / THD / SFDR

SNR reflects random noise; THD and SFDR expose harmonic distortion and spurs. Read datasheet FFT footnotes (input level, bandwidth, averaging) to avoid apples-to-oranges. If spectral purity matters, prioritize SFDR; for precision DC, focus on low noise density and ENOB.

Read more → Resolution
Power & Rails

Power scales with speed and channels. Rails set driver choices, input-range handling, and sequencing; leave thermal margin for hot environments. For battery or tight thermal budgets, compare energy-per-sample, not just “typical power” lines.

Read more → Front-End & Vref
Package & Temp

QFN is assembly-friendly and compact; BGA helps pin-count and signal integrity but complicates rework. Confirm stencil, paste, and reflow constraints, and choose the right temperature grade (Industrial or AEC-Q). Prefer families with footprint-compatible options.

Read more → IC selection policy
Availability & Risk

Screen NRND/EOL and lifecycle stability early, and line up second-source candidates. Ask for indicative lead-time windows and MOQ/Cut-Tape options. Favor pin-compatible families and plan a swap test (timing, noise, codes) before committing a layout.

Read more → Supply strategy
Clock & Jitter

Aperture/clock jitter converts to SNR loss proportional to input frequency—harmless at low kHz, severe at MHz. Set a jitter budget from required SNR, isolate clocks from noisy loads, and keep references clean and well-decoupled.

Read more → Anti-alias

Find Your Path by Scenario

Low-speed sensing (temperature / pressure / bridge / RTD)

Low-bandwidth sensing benefits from higher effective resolution and a quiet reference. Keep full-scale range close to the signal and budget an anti-alias RC even at low rates.

ΔΣ 16–24-bit SPI SE / Diff
Risks: Vref noise, ground bounce, high source impedance → add buffering.
Read more → Front-End & Vref
Current / voltage sampling (power monitors, BMS, industrial DAQ)

General DAQ and power/current monitoring favor SAR for low latency and easy bring-up. Size the driver and anti-alias filter so the source sees a stable load at the sampling instant.

SAR 12–18-bit SPI Differential
Risk: AAF design & driver impedance matching.
Read more → Anti-alias
High-speed sampling (vibration, imaging, RF IF)

High-throughput work needs Pipeline/Flash and a link that carries the data while keeping channels synchronized. Clock quality and lane timing dominate final performance.

Pipeline / Flash LVDS / JESD204 Multi-channel sync
Risks: clock jitter, synchronization, throughput budgeting.
Read more → Interfaces
Audio capture (voice / music)

Audio chains typically use audio-grade delta-sigma with I²S/TDM framing and well-managed references and clocks. This page doesn’t expand details—see the types overview.

Audio ΔΣ I²S / TDM 16–24-bit
Risks: clock distribution, grounding, reference isolation.
Read more → Types
Isolated measurements (high common-mode / high voltage)

Use isolated front-ends and differential inputs with isolated power and careful return paths. Validate CMTI and creepage/clearance early to avoid late-stage redesigns.

Isolated front-end Differential Isolated rails
Risks: isolated supply noise, CMTI, creepage/clearance.
Read more → Front-End & Vref
A wordless dark-blue cover showing interchangeable ADC solution blocks to convey brand-neutral, replaceable design.
48h 3 deployable options Brand-neutral · No long SKU lists

We Don’t “Retail” Parts — we ship solutions

In 48 hours you’ll get “Primary / Conservative / Value” proposals, plus lead-time windows & stock trend, a dual-source compatibility review, and minimal-BOM nudges for the front-end and Vref.

What you’ll receive (48h)

Three deployable options
  • Primary (balanced performance/risk)
  • Conservative (robust & production-friendly)
  • Value (cost & replaceability)
Lead-time window & stock trend

Not a precise quote; shows week/month windows, trend, and risk drivers.

Dual-source strategy
  • Pin/function & package compatibility
  • Driver/interface (SPI/LVDS/JESD204) alignment
  • Form/fit/function risk notes
Front-end / Vref nudges (minimal BOM)
  • RC anti-alias near 0.3–0.4×fs; short loop, local ground
  • 10–100 Ω series before S/H when needed
  • Vref decoupling 10 µF ∥ 0.1 µF at the pin
  • Clean LDO/reference; avoid noisy digital rails

Representative vendors (examples only)

Analog Devices Texas Instruments Microchip Renesas NXP onsemi Infineon

We remain brand-neutral and avoid long SKU lists; exact parts are selected per your constraints and risk posture.

Why we don’t publish long part lists

  • Supply, packages, and silicon revisions change fast; public lists stale quickly.
  • We prioritize risk coverage & compatible alternates, not catalog volume.
  • Each proposal includes drop-in or near-drop-in alternates where practical.
*Lead-time windows and stock trends are indicative only and not a quote. Compatibility notes cover pin/function, electrical, and interface aspects at a proposal level.

Send your constraints — get 3 safe options in 48 hours

Keep it engineering-focused. Required fields marked with *.

Application & performance targets
Use nominal bits; we’ll translate to ENOB.
If you entered bandwidth, note Nyquist margin in “Notes”.
Signal & front-end
For ±V domain, enter magnitude (e.g., ±2.5 → max=2.5) and choose “±V”.
System & interfaces
Power, rails & package
Enter target upper limit.
Environment & quality
Supply & preferences
We’ll provide ranges & trend, not stock guarantees.
Attachments & notes
Max 10 MB per file. BOMs, schematics, or signal plots help.
Contact for 48h reply
We’ll return three safe options within 48 hours. You’ll get a confirmation by email/IM shortly.
We only use this information to propose parts and follow up on your request. No marketing lists.
ADC Types (SAR / ΔΣ / Pipeline / Flash)

Architecture sets speed, latency, and noise behavior. Pick a direction before shortlisting parts.

Read more →
Resolution / ENOB / SNR

Nameplate bits aren’t equal to effective bits. Relate ENOB and SNR to your accuracy target.

Read more →
Anti-Aliasing & Nyquist

Stop out-of-band energy from folding into baseband. Even low-speed sensors need the right filter.

Read more →
Interfaces (SPI / LVDS / JESD204)

Make sure your link can move the data: throughput ≈ fs × bits × channels / efficiency.

Read more →
MCU/DSC Internal vs External ADC

When the internal converter isn’t enough—consider noise, bandwidth, latency, and isolation.

Read more →
Errors & Linearity (INL/DNL/Missing Codes)

Understand what specs mean in practice and how to catch problems during bring-up.

Read more →

ADC IC Selection — FAQ

How many bits do I really need?
Start from the smallest meaningful change you must resolve, convert to %FS, and map to an ENOB target. Nameplate bits rarely equal ENOB; reference stability and grounding dominate early errors. Read more →
SAR vs Delta-Sigma: where should I start?
SAR fits low-latency, general-purpose MS/s ranges; delta-sigma favors higher effective resolution at lower bandwidth. Choose by bandwidth and latency first, then shortlist by noise and power. Read more →
Do I need simultaneous sampling for multi-channel?
If phase alignment matters (e.g., motor control, vibration arrays), use simultaneous-sampling or alignable apertures. Otherwise, multiplexed SAR can suffice with proper timing and front-end buffering. Read more →
What interface should I use at higher sample rates?
Estimate throughput ≈ fs × bits × channels / efficiency. SPI is simple but tops out quickly; LVDS increases lanes; JESD204 scales cleanly at high rates with clocking discipline. Read more →
Can I swap vendors later without a redesign?
Aim for pin/footprint compatible families, but expect differences in drivers, references, and digital codes. Plan a second-source shortlist and validate timing, noise, and calibration before committing. See supply strategy →
Ersa

Anastasia is a dedicated writer who finds immense joy in crafting technical articles that aim to disseminate knowledge about integrated circuits (ICs). Her passion lies in unraveling intricate concepts and presenting them in a simplified manner, making them easily understandable for a diverse range of readers.