ADC vs DAC: What’s the Difference?

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ADC vs DAC: What’s the Difference?

Resolution–speed trade space highlighting the region where R-2R DACs are a good fit versus areas favoring Current-Steering or Delta-Sigma architectures.

In short, ADCs and DACs do opposite jobs: an ADC turns analog to digital, a DAC turns digital to analog. On the ADC side you protect the sampler with an anti-aliasing filter, a stable Vref, and clean clocking; on the DAC side you smooth the stair-stepped output with a reconstruction (anti-imaging) filter and a suitable output driver. The practical focus differs too: ADC choices revolve around sampling rate, input bandwidth and ENOB, interface throughput (SPI/LVDS/JESD204) and conversion latency; DAC choices lean toward update rate, THD+N/linearity, output range/drive, and common control links (SPI/I²C). For small-batch builds and bring-up, start by measuring: use an ADC to close the loop on sensors and diagnostics; add a DAC when you must generate or bias—waveforms, set-points, or actuators. At very low speeds, PWM plus an RC filter can stand in for a simple DAC, as long as ripple and accuracy limits are acceptable.

Want to learn “What is a ADC?” Read the definition →

Want to learn “What is a DAC?” Read the definition →

At a Glance

ADC measures analog into digital codes; DAC creates analog from digital data—the directions are opposite.

ADC protects sampling with anti-aliasing ahead of the converter; DAC smooths steps using reconstruction, anti-imaging filters.

ADC Vref sets LSB scale for codes; DAC reference or full-scale sets output span and drift.

Delta-Sigma architectures trade latency for in-band noise shaping; other families balance speed, latency, and noise differently.

ADC links favor SPI, LVDS, or JESD204 for throughput; DAC control commonly uses SPI or I²C.

Use ADCs for measurement, sampling, and feedback; use DACs for actuation, waveform synthesis, and analog set-points.

When to Use Which

For sensors, tuning, and data logging, use an ADC to close the measurement loop.

For waveforms, set-points, audio, or actuators, use a DAC with reconstruction filtering.

At low speed and relaxed linearity, PWM plus an RC can replace a simple DAC, with ripple limits.

Resolution: stable 12–16-bit ENOB favors external; low effective bits often suit MCU internal.
Bandwidth: high rate, many channels, or low latency push external; slow single-channel may fit internal.
Isolation/Noise: harsh EMI or mixed grounds suggest external converters with robust front-end and reference.
Linearity/THD+N: tight distortion or accuracy budgets favor external; relaxed specs often accept internal.
Interfaces: when SPI/I²C resources or throughput are constrained, external parts simplify timing and bandwidth.

ADC chain diagram: sensor → anti-alias filter → buffer → sample-and-hold → ADC → digital codes. — ADC: Sensor → Anti-alias RC → Driver/Buffer → S/H → ADC → Digital

Condition analog before sampling—buffer the source, filter out-of-band content, and hold a stable level for conversion.

High source impedance starves the sampling capacitor, causing droop and distortion.
Noisy or poorly decoupled Vref introduces code wander and ENOB loss.
Clock jitter degrades SNR at higher input frequencies.

Place RC anti-aliasing and a low-noise buffer ahead of the ADC input.
Decouple the local reference with 10 µF ∥ 0.1 µF at the pins.

Don’t

Drive the sampling cap through long wires or high impedance.
Feed reference or clock from noisy USB rails or switching noise.

DAC chain diagram: digital codes → DAC core → reconstruction filter → buffer/driver → analog output. — DAC: Digital → DAC Core → Reconstruction Filter → Driver → Actuator

Reconstruct smooth analog from codes—filter zero-order-hold steps and drive the load cleanly.

ZOH steps and images leak without reconstruction, creating high-frequency artifacts.
Output buffer slew or linearity limits inflate THD+N and blunt fast edges.
Load and ground bounce shift bias and couple noise across domains.

Add a properly designed reconstruction or anti-imaging filter after the DAC.
Select a driver with bandwidth and slew rate matched to load and range.

Don’t

Drive heavy loads, motors, or long cables directly from the DAC pin.
Ignore return paths and ground segregation near the analog driver.

What to watch on ADCs

Effective bits reflect real noise and errors; datasheet resolution is only ideal.
SNR sets the quantization floor; at high input frequencies, jitter often dominates.
Higher sampling reduces alias hazards and latency, but stresses interface data throughput.
Driver and anti-alias filter must pass the band without gain or phase droop.
Pipeline and delta-sigma add group delay; account it in loops and multiplexing.

What to watch on DACs

Output granularity is set by bits; analog noise limits how many are usable.
Linearity, reference ripple, and driver limits largely define overall THD+N performance figures.
Settling and glitch energy bound usable rate; zero-order hold creates spectral images.
Headroom, load current, and impedance set swing; most applications require a buffer.
Passband ripple, stopband depth, and phase delay shape fidelity in control or audio.

Resolution / ENOB / SNR

Interfaces & Throughput

ADC

SPI delivers simple framing at modest rates; channel count is limited by throughput and controller timing.
LVDS uses high-speed differential pairs to cut pin count; layout, pair skew, and EMI dominate risks.
JESD204 provides deterministic multi-lane latency for wideband, synchronized, multi-channel converters and coherent sampling.

DAC

SPI or I²C are common control links; practical update rate is bounded by bus speed and settling.
High-speed waveform DACs use LVDS or parallel paths; board skew and crosstalk grow quickly.
Shared clock jitter maps directly to SNR and spurs; isolate, buffer, and distribute clocks carefully.

Note: DAC interface timing and throughput considerations are largely the same principles discussed on the interfaces page.

Interfaces & Throughput

FAQ

Is a DAC just the reverse of an ADC?

They run in opposite directions, but the chains are not symmetric. On the ADC side you protect sampling with anti-alias filters, a quiet reference, and clean clocking. On the DAC side you smooth zero-order-hold steps, manage distortion and drive. Learn the mechanics here.

Do ADC and DAC need the same resolution?

Not necessarily. Size resolution to the system error budget and bandwidth. ADC effectiveness depends on ENOB, noise, and jitter; DAC usefulness depends on THD+N, load behavior, and reconstruction filtering. Chase usable performance, not nominal bits, then balance data rate and latency.

Why does a DAC need a reconstruction filter?

A DAC’s zero-order hold produces stair-stepped output and spectral images above half the update rate. A reconstruction (anti-imaging) filter smooths steps, rejects images and glitches, and improves audible or control fidelity. It also limits out-of-band energy that can alias elsewhere in a system.

Can PWM replace a DAC?

Sometimes. At low speeds with relaxed linearity, PWM plus an RC filter can approximate a simple DAC. Expect ripple, output impedance, and limited dynamic range; precision, wideband, or low-noise outputs still require a real DAC architecture and a proper reconstruction stage.

When to choose external over MCU-integrated?

Pick external parts when you need higher ENOB, wider bandwidth, tighter linearity or THD+N, better isolation, or deterministic latency. MCU-integrated converters suit slow, single-channel, noncritical roles where board space, cost, and simplicity dominate. Evaluate interfaces and throughput, too.

Need parts that actually ship?

Send your specs or BOM and get three safe options in 48 hours—ADC/DAC choices with indicative lead time, price range, and basic front-end/driver notes.

3× options: compatible alternatives with clear risk notes.
Availability insight: indicative lead-time and price ranges from real channels.
Engineering hints: front-end/Vref/driver tips for quick bring-up.

Submit your BOM (48h) See IC selection guide

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