Analog-to-Digital Converter (ADC) Guide: Types, INL/DNL & IC Selection

An analog-to-digital converter (ADC) samples a voltage and outputs an n-bit code. Types: SAR (≤5 MS/s), ΔΣ (best SNR at low BW), Pipeline (tens–100s MS/s). INL vs DNL: DNL < −1 LSB ⇒ missing codes; always state endpoint vs best-fit. Choose an external ADC over MCU ADC for >1 MS/s, stable ENOB, isolation, or tighter linearity.

ADC Types: SAR vs ΔΣ vs Pipeline
INL vs DNL & Missing Codes
Offset-Binary vs Two’s-Complement
External ADC vs MCU ADC

What is an ADC?

An analog-to-digital converter (ADC) samples a real-world voltage or current and encodes it as an n-bit digital code referenced to V_ref. This analogue-to-digital process lets software measure physical signals with predictable resolution, timing, and accuracy for control, data acquisition, and signal processing.

Sample — capture the input at a defined rate (sample frequency).
Hold — briefly stabilize the voltage so the converter can compare it reliably.
Quantize — pick the nearest level among 2ⁿ codes relative to V_ref.
Encode — output the binary word to the digital domain (e.g., SPI/LVDS/JESD204).

Quantization model (unipolar; full-scale = FS)

LSB = FS / 2ⁿ (top code corresponds to FS − 1 LSB, not +FS)
Uniform quantization noise (rms) ≈ LSB/√12
SNR_q for a full-scale sine ≈ 6.02·n + 1.76 dB
ENOB ≈ (SNR − 1.76)/6.02 → converts measured SNR back into “effective bits”

Polarity & coding affect how you interpret the code: straight binary fits unipolar (0…V_ref); bipolar inputs use offset-binary (zero at mid-code) or two’s-complement (MSB as sign, DSP-friendly). A wrong assumption shifts zeros or flips signs—double-check the output format before math. See Codes & Polarity.

Engineering essentials

Reference & driver: keep V_ref,rms + driver noise « 0.5·LSB_rms; unstable drivers show up as DNL/ENOB loss.
Settling: for SAR, the input RC must settle to ~0.5·LSB within the acquisition window, otherwise effective bits drop.
Clock jitter: limits high-frequency SNR: SNR_jitter ≈ −20·log₁₀(2π·f_in·σ_j) (dB).
Bandwidth: obey Nyquist with an anti-alias filter; ΔΣ often tolerates gentler analog filtering.

Resolution (n) sets LSB size, while sample rate and the core architecture (SAR/ΔΣ/pipeline/flash) determine speed and latency. With a clean reference and a properly designed front end, the digital codes track the input within the converter’s specified accuracy. Learn more in How an ADC Works and ADC Types.

Analog waveform → Sample-and-Hold → Quantizer vs Vref → Encoder → n-bit output; maximum code equals FS minus 1 LSB — Concept: waveform enters S/H, is quantized against **V_ref**, then encoded to n-bit codes. The maximum code corresponds to *FS − 1 LSB*.

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How an ADC Works

How does an analog-to-digital converter work? An ADC turns a changing voltage into an n-bit code via track/hold → compare → encode. A sample-and-hold (S/H) captures the input at a defined instant; the core (SAR, delta-sigma, pipeline, or flash) compares the held level to V_ref and selects the nearest of 2ⁿ codes; digital logic formats the result for SPI, LVDS, or JESD204. In real designs, S/H aperture and jitter, driver settling, and reference noise largely determine usable ENOB and bandwidth.

Sample & Hold — track the waveform, then switch to hold; the held voltage must settle within ~0.5 LSB of its final value.
Compare & Quantize — the core compares the held level against thresholds derived from V_ref and assigns the nearest code.
Encode & Transfer — the n-bit word is aligned (straight/offset-binary/two’s-complement) and transferred over SPI/LVDS/JESD204.

Architectures in practice

SAR — binary search on a capacitor DAC: MSB→LSB decisions during the hold window. Deterministic latency; requires the driver+RC to settle each cycle or ENOB/DNL suffer.
ΔΣ — integrator → comparator → 1-bit DAC closed loop creates a bitstream; a digital decimation filter low-passes/downsamps to yield high ENOB. Added group delay is the trade-off.
Pipeline — cascaded sub-ADCs/sub-DACs resolve a few bits per stage; results are time-skewed and digitally aligned. Delivers multi-MSPS to GSPS with fixed multi-stage latency; clock quality is critical.
Flash — parallel comparators against a resistor ladder decide all bits in one step. Near-zero latency at the cost of power and lower resolution.

Quantization & timing essentials

LSB = FS / 2ⁿ; the maximum code represents FS − 1·LSB (not +FS).
Uniform quantization noise (rms) ≈ LSB/√12; ideal SNR_q (full-scale sine) ≈ 6.02·n + 1.76 dB.
Aperture jitter limits HF SNR: SNR_jitter ≈ −20·log₁₀(2π·f_in·σ_j) dB. At higher f_in, even tens of femtoseconds matter.
SAR settling: ensure input RC settles to ~0.5 LSB within the acquisition window (t_acq), otherwise effective bits drop and DNL widens.

Design tips: obey Nyquist with a proper anti-alias filter; size the driver/RC to meet the S/H settling target; minimize clock jitter to preserve high-frequency SNR; and verify ENOB at the intended sample rate and bandwidth. Learn more in ADC Types and Front-End & Vref.

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Analog waveform → sample-and-hold → comparator/quantizer → encoder → n-bit output vs Vref; settling and aperture jitter affect ENOB — Signal path: S/H captures the input; the core quantizes against **V_ref**; digital logic encodes for the interface. Settling and aperture jitter bound achievable ENOB.

Reference: Wikipedia — Analog-to-digital converter (general overview).

ADC Types (SAR / ΔΣ / Pipeline / Flash)

A ΔΣ ADC first converts the analog input into a 1-bit bitstream using an integrator → comparator → 1-bit DAC feedback loop. The loop noise-shapes quantization error out of band. A digital decimation filter then low-passes and downsamples the bitstream, trading bandwidth for high ENOB. The trade-off is latency (group delay) from the digital filter; practical group delay often equals roughly (filter_length−1)/(2·f_out), so control loops must budget it.

Best for low-bandwidth precision (weighing, energy metering, instrumentation)
Tune OSR / filter type to balance noise vs update-rate and latency; higher OSR lowers in-band noise but increases delay/compute.

SAR (Successive Approximation) — Low latency, deterministic timing, simple drive; typically 10–18-bit, tens of kS/s to ~2 MS/s. Interfaces: SPI/CMOS parallel. Best for precision sensing, MCU/FPGA control loops, multiplexed DAQ. Watch-out: ensure driver+RC settle within the acquisition window (t_acq) to ~0.5 LSB; otherwise ENOB drops and DNL widens.
ΔΣ (Delta-Sigma) — Very high resolution/ENOB with strong 50/60-Hz rejection; bandwidth is lower and latency higher. Typical 16–24-bit, Hz–hundreds of kS/s effective output rates. Interfaces: SPI/I²S (audio). Best for metering/audio/precision DC. Watch-out: account for decimation filter group delay and sinc/notch placement vs mains/line frequencies.
Pipeline — Multi-MSPS to GSPS with good SFDR/SNR for IF, communications and imaging; typical 8–16-bit, 5 MS/s–1 GS/s+. Interfaces: LVDS/JESD204( B/C ). Latency is several pipeline stages (fixed but non-zero). Watch-out: clock jitter and front-end driver linearity dominate high-frequency ENOB; plan deterministic sync for multi-channel.
Flash — Ultra-fast, near-zero latency but power-hungry with lower resolution (comparator count ≈ 2ⁿ−1). Typical 4–8-bit, hundreds of MS/s to multi-GS/s. Best for triggers, oscilloscope front-ends, radar/TOF. Watch-out: offset/power scale rapidly with bits; often used as sub-ADC inside hybrid/pipeline cores.

ADC type matrix: SAR, Delta-Sigma, Pipeline and Flash compared by rate, resolution, latency, power, interface and applications — Preview matrix (rate / resolution / latency / power / interface / applications) for the main *analog to digital converter types*; full table in the detailed guide.

Choose by required bandwidth, resolution/ENOB and latency, then verify front-end drive (settling, noise) and interface headroom (throughput, sync). Practical rules: control loops → SAR, precision DC → ΔΣ, IF/vision → Pipeline, extreme speed/trigger → Flash. For signal-chain context see Front-End & Vref and Interfaces.

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Resolution / ENOB / SNR

ADC resolution is the nominal bit depth (2ⁿ codes) that sets LSB size; ENOB is the measured effective bits once all noise and distortion are included at your actual sample rate and bandwidth. For a full-scale sine, the textbook link is ENOB ≈ (SNR − 1.76)/6.02; in practice you should prefer ENOB from SINAD (includes harmonics) when dynamic linearity matters.

ENOB from SNR vs from SINAD

ENOB_SNR ≈ (SNR − 1.76) / 6.02 — quantization + noise only

ENOB_SINAD ≈ (SINAD − 1.76) / 6.02 — includes distortion (recommended for AC specs)

Noise budget (rms, add in power)

Quantization (full-scale FS, unipolar): σ_q ≈ LSB/√12, where LSB = FS/2ⁿ.
Reference + driver: σ_ref, σ_drv from data/bench (refer to input); layout/PSRR and filtering dominate here.
Clock jitter (sine at f_in): SNR_jitter ≈ −20·log₁₀(2π·f_in·σ_j) dB → convert to σ and sum.
Total: σ_total² ≈ σ_q² + σ_ref² + σ_drv² + σ_jitter² (+ distortion as power for SINAD).

Architecture levers that move ENOB

ΔΣ (order = L): doubling OSR improves in-band SNR by ≈ (2L+1)·3 dB (first-order ≈ 9 dB, second-order ≈ 15 dB) at the cost of bandwidth and group delay (filter ENBW matters).
SAR: the input cap sees kT/C noise; σ_kT/C ≈ √(kT/C). To avoid an ENOB floor, choose C so that σ_kT/C ≪ LSB/√12 and ensure RC settling to ~0.5·LSB within t_acq.

Not full-scale? apply headroom penalty

The SNR formulas assume a full-scale sine. If your signal uses only a fraction α of FS (rms), effective SNR drops by 20·log₁₀(α) dB, lowering ENOB accordingly.

Example: using 50% FS (rms) costs ≈ 6 dB ≈ 1 bit of ENOB.

LSB = FS / 2ⁿ (examples at FS = 10 V):

8-bit → 10 V / 256 = 39.06 mV
12-bit → 10 V / 4096 = 2.441 mV
14-bit → 10 V / 16384 = 0.610 mV
16-bit → 10 V / 65536 = 0.153 mV

Change FS to your system range to scale results.

Quick reality checks

Ideal 16-bit SNR_q ≈ 6.02·16 + 1.76 ≈ 98 dB (full-scale sine).
Jitter crossover: at f_in=10 MHz, σ_j≈200 fs yields SNR_jitter≈98 dB → jitter starts to erase 16-bit advantage.
ΔΣ rule-of-thumb: a 2nd-order modulator gains ≈15 dB per 2× OSR until analog limits (V_ref, driver) dominate.

ENOB is impacted by anti-alias filtering and clock jitter as well as V_ref and driver noise. For context, see Front-End & Vref and Anti-Aliasing & Jitter. When dynamic range matters across frequency, prefer SINAD-based ENOB and verify at the target bandwidth with the intended windowing/FFT settings.

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Codes & Polarity

ADC output coding ties directly to signal polarity and downstream math. Straight binary targets unipolar ranges (0…FS) and maps codes from 000…0 to 111…1 (FS − 1 LSB). Offset-binary supports bipolar inputs (±FS) by shifting zero to mid-scale (100…0). Two’s-complement also covers bipolar ranges but encodes the sign in the MSB, which is friendly to DSP and fixed-point arithmetic. Match the format to your sensor polarity and MCU/FPGA interface; a wrong mapping causes zero-shift or inverted sign.

Range conventions (endpoints & mid-code)

Unipolar (Straight): codes 0…2ⁿ−1 map 0…FS − 1 LSB; no +FS code.
Bipolar mid-tread (Two’s-comp): zero has a single code (all 0s); negative full-scale is 100…0, +FS is 011…1 (= +FS −1 LSB).
Bipolar mid-rise (Offset-binary): zero occurs between two mid-codes; zero crossing toggles MSB.

Unipolar sensing (0–Vref) — current loop, light, single-ended pressure → use Straight.
True ± signals — centered op-amp, bridges, audio/vibration → prefer Two’s-complement for signed math.
Legacy boards or ADCs with Offset-binary — keep Offset-binary, or invert the MSB in firmware to obtain Two’s-complement.

Quick formulas (FS = full-scale, LSB = FS / 2ⁿ)

Straight: V = LSB × Code (Code ∈ 0…2ⁿ−1)
Offset-binary: V = LSB × (Code − 2ⁿ⁻¹)
Two’s-complement: interpret Code as signed S (if Code ≥ 2ⁿ⁻¹, S = Code − 2ⁿ), then V = LSB × S

Offset-binary ↔ Two’s-complement conversion ≈ invert MSB (i.e., Code XOR 2ⁿ⁻¹), then reinterpret.

Reliable conversions (with 16-bit examples)

Offset-binary → Two’s-comp: tc = ob ^ 0x8000 (bitwise MSB invert). Example: 0x8000 (0 V) → 0x0000.
Two’s-comp → Offset-binary: ob = tc ^ 0x8000. Example: 0x7FFF (≈ +FS−1 LSB) → 0xFFFF.
Straight → engineering volts (unipolar): V = (Code / (2^n − 1)) × FS (use 2^n−1 if codes reach top).
Bipolar Two’s-comp → volts: sign-extend → scale by LSB (= FS/2ⁿ).

3-bit intuition
STRAIGHT (unipolar):      000 → 0                 … 111 → +FS − 1 LSB
OFFSET-BINARY (bipolar):  100 → 0;   001 → −FS + 1 LSB;   111 → +FS − 1 LSB
TWO’S-COMPLEMENT (bipolar):000 → 0;   111 → −1 LSB;        100 → −FS

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End-point conventions vary slightly by device; “+FS” typically corresponds to FS − 1 LSB.

Straight binary vs offset-binary vs two’s-complement code mapping for unipolar and bipolar ADC outputs — 3-bit intuition: Straight maps 000→…→111 (unipolar); Offset-binary uses 100 as zero (bipolar); Two’s-complement encodes the sign in the MSB and centers numeric zero at 000.

Unsigned readout of a bipolar code shifts zero by half-scale.
Bit/byte alignment (left vs right; padding zeros) mismatched → gain/overflow errors.
Bit order & MSB inversion mixed up → stair-step artifacts and wrong sign.

Bring-up gotchas (save your weekend)

Sign extension: 24-bit Two’s-comp packed into 32-bit words must replicate the sign bit across the upper 8 bits; treating as unsigned shifts zero.
Justification: “left-justified 16-bit in 24-bit frame” changes LSB weight; firmware must track bit weight, not just field width.
Over-range: many ΔΣ/pipeline ADCs output “clamp codes” plus a status flag when |input| > FS; don’t average clamp codes—drop or mark them.
Status interleave: some devices interleave status/header bits with data; failing to strip them causes apparent missing-code patterns.

Two-point calibration (recommended)

Measure codes at two accurate references (V_L, V_H) to solve gain/offset and immunize endpoint conventions:

Gain = (V_H - V_L) / (Code_H - Code_L)
Offset = V_L - Gain × Code_L
Then convert any Code via V = Gain × Code + Offset (after format normalization).

Need LSB sizing and bit-depth context? For bus alignment and throughput planning, see Interfaces. For ENOB/SNR realities and non-ideal limits, see Resolution / ENOB / SNR.

Errors & Linearity

DNL quantifies each code’s step-width error; INL is the accumulated deviation from an ideal straight transfer. If any DNL < −1 LSB, codes disappear and monotonicity can break. Always state the reference: endpoint (line through 0/+FS endpoints) or best-fit (least-squares). Use ramp or code-density tests to separate true converter errors from front-end settling, reference noise, and clocking—then decide whether to calibrate or reselect.

Ideal 3-bit ADC transfer with uniform 1 LSB steps and no error — Ideal steps: each code = 1 LSB.

Non-ideal transfer with varying step widths (DNL) and cumulative deviation (INL) — DNL varies per step; INL accumulates vs the chosen straight line.

ADC missing code and non-monotonic segment when DNL < −1 LSB — DNL < −1 LSB → missing codes / non-monotonicity.

Quick relations (declare the reference line)

DNL[k] ≈ ΔV[k]/LSB − 1 (step k width vs ideal 1 LSB)
INL[k] = max_codes≤k |V[k] − V_ref-line[k]| / LSB, where ref-line is endpoint or best-fit
Code-density (histogram) method: DNL[k] ≈ N[k]/N̄ − 1; INL is the cumulative sum of DNL after removing average slope

Measurement that holds up in the lab

Ramp test: drive a highly linear ramp (stimulus linearity ≪ target INL); sample densely; fit endpoint for spec comparison and best-fit to reveal curvature (“bow”).
Code-density test: use a spectrally pure sine covering the range; expected counts N̄ are uniform; compute DNL per bin, then accumulate to INL. Dwell long enough to average transition noise.
Transition noise (σ_T): LSB_rms flicker around a DC threshold. Large σ_T can hide real DNL—average many hits per code or add tiny dither to estimate the mean transition level.
De-embedding: verify driver settling and clock jitter first; otherwise you measure the front end, not the ADC.

Error fingerprints by architecture

SAR: capacitor mismatch → gentle “bow” INL; distinct kinks at binary boundaries (1/2, 1/4 FS…); inadequate RC settling shows as apparent negative DNL near fast transitions.
ΔΣ: dynamic element matching smooths DNL; nonlinearity often appears as idle tones/modulator residue in the spectrum; INL/DNL curves tend to be smooth.
Pipeline: residue amp gain error and switch injection → periodic INL texture; inter-channel mismatch in parallel systems presents as distortion and phase skew.
Flash: comparator offsets/threshold drift → local DNL bumps; temperature drift moves thresholds—calibrate periodically.

From “spec miss” to “in-spec”

Gain/offset: two-point calibration removes endpoint error (see Codes & Polarity).
Segmented linearization: fit piecewise slopes or use a LUT over anchor codes to “straighten” the bow; very effective for SAR/pipeline.
Dither + average: inject small noise/jitter to linearize transition thresholds (reduces idle tones, improves effective DNL).
Thermal/aging: measure at multiple temperatures and fit coefficients for temperature compensation.

Measure in sub-ranges (avoid saturation) to localize wide/narrow codes; for SAR, inspect near binary boundaries.
Front-end sanity: driver bandwidth/stability, S/H settling, V_ref noise/drift (PSRR and layout).
Timing & I/O: clock jitter/sync; bit alignment, endianness, and status-bit stripping to avoid “fake” missing codes.
Spec language: confirm the vendor’s INL/DNL definitions (endpoint vs best-fit, temperature/rate conditions, test method).

For signal-chain context see Front-End & Vref and Resolution / ENOB / SNR. Read more details in the chapter below.

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Front-End & Vref

How to convert analog to digital reliably is mostly a front-end and reference problem: constrain bandwidth before the ADC, ensure the driver settles the ADC input network within the acquisition window, and keep V_ref quiet and low-impedance across the conversion spectrum. Choose architecture for latency/ENOB, but allocate error budget to driver noise + settling and reference noise + impedance. Verify ENOB at the intended rate, bandwidth and clock/jitter with your final PCB layout.

Anti-alias filter — place the cutoff where the useful band comfortably clears Nyquist and where the driver can still settle. For SAR, a small series-R + C to ground at the ADC pin also absorbs kickback; for ΔΣ, gentler analog filtering is fine, but verify digital filter notches vs mains.
Sample rate — ≥2× signal bandwidth is the floor; 2.5–5× is typical to cover transition bands and allow relaxed analog filters. Check aperture jitter vs highest tone (see jitter card in Anti-Aliasing & Jitter).
ADC architecture — SAR (deterministic, simple drive); ΔΣ (high ENOB, group delay); Pipeline (MSPS–GSPS, multi-stage latency); Flash (extreme speed). Architecture sets input behavior: e.g., SAR presents a switched-cap load during t_acq, pipelines require clean sampling clocks and low reference impedance during MDAC events.
Vref & driver — keep Vref_rms + driver noise « 0.5·LSB_rms. Use a buffer or dedicated reference driver so Vref looks like a wideband low-Z source. For the driver, ensure loop stability into the ADC’s capacitive load and meet settling to ~0.5-LSB at the end of t_acq.
Readout & calibration — align bit/byte order and coding; average or decimate appropriately; apply zero/gain calibration and, when needed, piecewise linearization to remove residual bow. Validate across temperature and supply corners.

Sensor → anti-alias RC → driver (GBW, stability) → ADC S/H (Cin, t_acq) with Vref noise budget → digital interface → calibration — Practical signal chain from sensor to firmware calibration; highlight RC settling, driver GBW/stability and Vref noise.

Quick refs

LSB = FS / 2ⁿ
RC settling (SAR input): t_settle ≈ RC·ln(1/ε). For ε ≈ 0.5·LSB/FS, a practical bound is RC ≲ t_acq / ((n+1)·ln2) (includes driver + source R and the ADC S/H Cin).
Driver bandwidth: first-order closed-loop f_cl ≈ GBW/A_CL → meet f_cl >rsim ln(1/ε)/(2π·t_settle). Add margin for phase-lead networks used to stabilize capacitive loads.
Reference noise target: Vref_rms (integrated over the converter’s effective bandwidth) ≲ LSB_rms/4. Use small (µF) + bulk (10–47 µF) decoupling and Kelvin connect Vref/GND pins.
Source impedance: R_S,max ≈ t_acq / (k·C_in) with k ≈ (n+1)·ln2; include filter R and driver Rout.

For jitter and filtering details see Anti-Aliasing & Jitter; for architecture trade-offs see ADC Types; for LSB/ENOB math see Resolution / ENOB / SNR.

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Anti-Aliasing & Clock Jitter

Anti-aliasing is a budgeting problem, not just a cutoff choice. Define the in-band SNR/ENOB target, then ensure the analog filter plus any digital decimation leaves out-of-band energy « your noise floor before sampling. For SAR, the filter must also damp S/H kickback so the driver still settles by the end of the acquisition window; ΔΣ converters can use gentler analog filters but require aligning the analog passband with the decimator’s droop/notches. Clock jitter limits high-frequency SNR, so size the clock tree (source, PLL, distribution) from the top-end input frequency backward. Verify with spectra on the final PCB, not just in simulation.

Cutoff & order — choose f_c so the useful band has guard margin to Nyquist; for SAR a practical start is f_c ≈ 0.4–0.45·f_s to balance alias rejection and settling. For ΔΣ, a first/second-order RC is often adequate—confirm passband droop versus the decimator.
Stopband — set required attenuation from an alias budget: require ∑_k≠0∫_band|H(f±k·f_s)|²S_x(f)df « in-band noise. As a rule of thumb: ~60 dB for 12–14-bit, ~80 dB for 16-bit systems with wide out-of-band content.
Phase/group delay — Bessel/low-order for control and time-domain shape; Butterworth/Chebyshev/Elliptic when amplitude flatness and stopband density dominate. Verify ringing vs S/H acquisition windows.
Clock quality — size RMS jitter from the highest input tone; keep the clock’s supply/ground isolated from the digital interface; integrate PLL phase noise over the converter’s aperture bandwidth to get σ_j.

Jitter-limited SNR (sine approximation)

SNR_jitter ≈ -20·log₁₀(2π·f_in·σ_j) (dB)

f_in: highest useful input frequency; σ_j: RMS clock jitter.

Design recipes that survive bring-up

SAR input damping: a small series-R (≈10–100 Ω) + shunt-C at the ADC pin both low-passes and tames S/H kickback. Choose C so the driver still meets 0.5-LSB settling by the end of t_acq; then tune R to stabilize the op-amp into the effective C_in.
Guard band: leave 0.1–0.2·f_s between f_c and Nyquist to keep stopband growth feasible as you raise f_s or channel count.
ΔΣ alignment: know your decimator: CIC/half-band chains have passband droop—either compensate in DSP or nudge the analog f_c lower so system gain is flat in-band and steep near the first image.
Jitter budget to ENOB: ENOB_jitter ≈ -log₂(2π·f_in·σ_j). Example: at 200 kHz, σ_j=100 fs → ENOB_jitter≈15.7 bits; at 2 MHz, the same clock only supports ≈12.7 bits.
PLL to pins: integrate phase-noise L(f) to σ_j; keep the clock tree on a quiet regulator, short return paths, and differential where possible; avoid routing near high-di/dt digital I/O.

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Baseband with anti-alias low-pass; images at k·f_s ± f_in; jitter broadens the high-frequency tone — Anti-alias LPF constrains the band below Nyquist; images appear at k·f_s ± f_in. Jitter broadens tones and reduces HF SNR.

Interfaces (SPI / LVDS / JESD204)

Pick the ADC interface by required throughput, channel count, synchronization and implementation effort. SPI suits low/medium rates with simple wiring but is bounded by SCLK and readout windows. LVDS scales to hundreds of Mb/s using DDR and multiple differential pairs. JESD204 (B/C) handles multi-Gb/s with deterministic latency and multi-channel sync via lanes and SYSREF/LMFC. Start from a quick bandwidth estimate, then plan lane count, per-lane rate and clock quality; finally confirm bit alignment and coding format on the wire.

throughput (bps) = f_s × bits × channels / efficiency

efficiency accounts for coding/overhead: SPI (depends on status/idle gaps), LVDS (~0.95–1.00 with framing), JESD204B 8b/10b ≈ 0.80, JESD204C 64b/66b ≈ 0.97.

Example A — SPI boundary: f_s=500 kSPS, 12-bit, 8 ch, η=0.80 → throughput ≈ 60 Mb/s. Many SPI hosts sustain 20–40 Mb/s; for continuous streaming consider LVDS/parallel.
Example B — LVDS feasible: f_s=5 MSPS, 16-bit, 2 ch, η=0.95 → ≈ 168 Mb/s. One DDR pair can carry this with margin; mind alignment and jitter.
Example C — JESD planning: f_s=125 MSPS, 14-bit, 2 ch, η=0.97 → ≈ 3.61 Gb/s. If lane max=2.5 Gb/s → need 2 lanes (~1.81 Gb/s per lane).

ADC interface bandwidth: SPI vs LVDS vs JESD204 using throughput = f_s × bits × channels / efficiency — Use the throughput formula to size SCLK, LVDS pairs or JESD204 lanes before detailed timing closure.

SPI reality check

Effective bit budget includes payload + status/channel bits + padding. A practical lower bound for clock is:

SCLK ≥ fs × (bitspayload + overhead)

Check CPOL/CPHA, CS de-assert gaps, DMA window (continuous frames often cap at 20–40 Mb/s on MCUs).
Delta-sigma + SPI example: f_s=32 kSPS, 24-bit, 4 ch, η=0.70 → ≈ 4.4 Mb/s (comfortably within SPI).

LVDS source-synchronous checklist

100 Ω terminations; control intra-pair and inter-pair skew (e.g., <50–100 ps).
Use training/bit-slip if provided; verify lane polarity (P/N swaps) and frame markers.
Clock quality matters; keep jitter/SSO and return paths under control.

JESD204 quick notes

B: 8b/10b (η≈0.80); C: 64b/66b (η≈0.97) — higher efficiency, higher lane headroom.
Subclass 0/1/2 define deterministic latency; SYSREF aligns LMFC across devices.
Lane rate ≈ throughput / L; keep 10–20% margin. Example (high-speed): f_s=250 MSPS, 14-bit, 4 ch, η=0.97 → ≈ 14.44 Gb/s total → L=6 gives ~2.41 Gb/s per lane.
Params (illustrative): M=channels, L=lanes, F=octets/frame, S=samples/frame, N′=bits/sample after alignment, K=multiframes.

Efficiency quick look

SPI ≈ 0.60–0.90 (gaps/status) · CMOS parallel ≈ ~1.00 · LVDS ≈ 0.95–1.00 · JESD204B ≈ 0.80 · JESD204C ≈ 0.97

Format (offset-binary vs two’s-complement), left/right alignment and status bits change effective bit-rate.

SI: length-match differential pairs, define return paths, review eye diagrams/headroom.
Clocking: jitter limits HF SNR (see Anti-Aliasing & Jitter); isolate clocks and power domains.
Bring-up: don’t push data until LVDS framing or JESD CGS/ILAS is locked; verify endianness/bit order.

See Codes & Polarity for data mapping, Resolution / ENOB / SNR for bit-depth context, and Anti-Aliasing & Jitter for clock quality impacts.

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ADC vs DAC · At a Glance

ADC and DAC solve opposite problems. Use this quick side-by-side to decide which constraints dominate your design and where to budget noise, jitter, and bandwidth.

ADC (Analog → Digital)

Goal — Sample, quantize, encode real-world signals.
Architectures — SAR, ΔΣ, Pipeline, Flash.
Bottlenecks — Anti-aliasing, S/H settling, V_ref noise, clock jitter.
Specs — ENOB/SNR/SFDR, INL/DNL, latency, sample rate.
Front end — Low-impedance driver + RC for SAR kickback; clean reference and low-jitter clock.

DAC (Digital → Analog)

Goal — Reconstruct voltage/current from digital codes.
Architectures — R-2R, current-steering, ΔΣ.
Bottlenecks — Glitch impulse, settling, ZOH images, output buffer stability.
Specs — Resolution/ENOB, SFDR/THD, INL/DNL, update rate.
Back end — Reconstruction low-pass, RF-stable buffer (GBW/SR), image/EMI control.

View chapter

Design heuristics

Measurement/control focus → start with ADC front end, jitter budget, and anti-aliasing.
Waveform/synthesis focus → start with DAC circuits, reconstruction filter, and glitch/settling limits.
High-throughput multi-channel → consider SPI/LVDS/JESD204 sync, framing, and per-lane headroom.

ADC front-end: anti-alias filter, low-noise Vref, SAR driver with RC settling and low-jitter clock — ADC front end emphasizes anti-aliasing, low-noise reference, SAR kickback control, and low-jitter clocking.

DAC back-end: reconstruction low-pass, RF-stable buffer (GBW/SR), and image suppression at multiples of the update rate — DAC back end emphasizes reconstruction filtering, RF-stable buffering, and image suppression.

Next: dive into DAC principles & types, or jump straight to Circuits & Specs and 10 MHz planning.

Raspberry Pi · Adding an External ADC

Raspberry Pi boards lack an on-chip ADC. To implement sensing on a Raspberry Pi analog to digital converter setup, add a small external ADC over SPI or I²C, then size the front end so sample/hold kickback and reference noise don’t dominate your ENOB, sample rate, and latency.

Quick picks — MCP3008/3208 (SPI, 10–12-bit) for basic sensing; ADS1115 (I²C, 16-bit) for higher resolution at low rates; AD400x / ADS888x for precision SAR up to MSPS (SPI; requires a proper driver and RC).
Throughput reality — effective per-channel rate ≈ SCLK·efficiency / (bits·channels) (SPI) or I²C_rate / frame_bits. Use SPI DMA for continuous capture; I²C is simpler but slower.
Front end — add a small series-R (≈10–100 Ω) + shunt-C at the ADC pin (SAR) to tame S/H kickback; keep source impedance low so codes settle within t_acq.
Power & reference — use the ADC’s own V_ref with local decoupling. Avoid deriving precision V_ref directly from noisy USB 5 V rails.
Logic & wiring — Pi logic is 3.3 V; confirm CPOL/CPHA; keep SCLK/MISO/MOSI/CS short and well-returned; consider shielding for long sensor leads.

Raspberry Pi SPI wiring to an external ADC with reference routing, driver RC and decoupling — SPI wiring from Raspberry Pi to an external ADC, highlighting 3.3 V logic, decoupling, reference routing and SAR RC network.

Rule-of-thumb setups

I²C, high resolution (slow): ADS1115 @ 128–860 SPS for temperature/pressure; on-board PGA simplifies scaling.
SPI, mid-speed: MCP3008/3208 @ tens–hundreds kSPS; enable SPI DMA; average/decimate for noise.
SPI, precision/MSPS: AD400x / ADS888x @ 500 kSPS–2 MSPS; pair with a low-noise driver op-amp and RC sized per Front-End & Vref.

Throughput & per-channel rate · worked examples

MCP3008 (10-bit, SPI, 8 ch): assume SCLK=12 MHz, efficiency≈0.8 (command/status/padding). Per-channel ≈ 12e6·0.8 / (10·8) ≈ 120 ksps/ch ideal. Add 10–20% margin ⇒ plan ≈ ~100 ksps/ch.
AD4000-class SAR (16–18-bit, SPI, 1 ch): at SCLK=24 MHz, eff≈0.9, ~20 bits on the wire ⇒ ≈24e6·0.9 / 20 ≈ 1.08 MSPS. With acquisition/convert overhead and settling, practical ≈ 0.5–1.0 MSPS.
ADS1115 (I²C, 16-bit): limited by ODR (128–860 SPS); bus speed is not the primary limit. Digital-filter group delay sets latency.

Tip: use SPI DMA for continuous capture; verify descriptors cover bursts without CPU stalls to avoid periodic data gaps.

View chapter

Per-channel throughput estimate for SPI and I²C external ADCs on Raspberry Pi — Per-channel rate ≈ SCLK·efficiency / (bits·channels) (SPI) or I²C_rate / frame_bits. Typical SPI efficiency 0.7–0.95; I²C depends on framing.

MCU/DSC Internal vs External ADC

Use an MCU’s built-in ADC for utility sensing; step up to an external device when you need guaranteed ENOB at speed, tighter linearity, true multi-channel concurrency, isolation, or high-throughput interfaces. The call is rarely about “bits on the datasheet” alone—budget for settling, reference quality, aperture jitter, and multiplexing penalties. The mini decision tree below turns those constraints into a crisp choice.

Quick decision tree

Resolution / dynamic range — target ≤12-bit (ENOB ≲10.5) → likely MCU internal. Target ≥16-bit or ENOB ≥14.5 (SNR ≳90–92 dB) → external ΔΣ / precision SAR. Treat MCU “12/14-bit” as typical, not guaranteed across rate/temperature.
Bandwidth / sample rate — f_s ≤ 200 kSPS with few channels → internal. Need ≥1–2 MSPS per channel, or concurrent ≥0.5 MSPS/ch without inter-channel skew → external SAR / pipeline / flash. Remember MUXed MCU ADCs deliver per-channel rates = f_s/N and add settling errors at high source Z.
Isolation / common-mode — kV isolation, high common-mode or shunt measurements → external isolated modulator/ADC with digital isolation and isolated power; MCU ADCs rarely meet error + creepage at temperature.
Linearity / precision — INL ≤ ±1 LSB@N-bit or very low drift → favor external (low-noise V_ref, buffer, and specified INL method). MCU references often have higher tempco and wider trim spread.
Interface / throughput — SPI within host limits → internal or external-SPI. Need LVDS/JESD204/parallel, deterministic multi-channel sync, or laneable Gb/s throughput → external.

“Must go external” thresholds

#1 Precision: ENOB ≥ 15-bit or SNR ≥ 93 dB / THD ≤ −100 dB; need guaranteed INL spec (endpoint/best-fit) across temp and rate.
#2 Speed: f_s ≥ 2 MSPS on any channel, aggregate ≥ 200 Mb/s, or you must avoid MUX “dead time” & settle errors → SAR/pipeline/flash with proper drivers.
#3 Isolation / concurrency: channel-to-channel isolation, simultaneous sampling (≥4 synchronous channels, phase skew < 10 ns), safety isolation or HV common-mode → isolated modulators or multi-channel simultaneous-sampling ADCs.
#4 Clock/jitter bound: at your highest tone f_in, MCU PLL jitter limits ENOB_jitter ≈ −log₂(2π·f_in·σ_j). If this undercuts target bits → external clocking/ADC.

Good fit for internal ADC: 0–V_ref (or 0–10 V after scaling), 10–12-bit utility sensing at ≤200 kSPS, 2–8 MUXed channels, no safety isolation, and tolerable INL of ±1–3 LSB. Keep source impedance low so the S/H settles in time, enable DMA for continuous capture, average/decimate for noise, trim zero/gain vs temperature, and validate that the MCU’s V_ref noise/PSRR/jitter meet your system ENOB at the chosen rate.

View chapter

Decision tree: resolution, bandwidth, isolation, linearity, interface → choose MCU/DSC internal ADC or external ADC (Delta-Sigma / SAR / Pipeline / Flash) — Five-factor decision flow from requirements to internal vs external—and to the right external ADC class when needed.

See Resolution / ENOB / SNR for bit-depth targets, Front-End & Vref for driver/reference budgeting, and Interfaces for throughput planning.

DAC Basics · Circuits & Specs

A digital to analog converter circuit reconstructs voltage or current from digital codes. Pick the DAC architecture by required bandwidth and linearity: R-2R ladder and current-steering suit fast, wideband updates; ΔΣ offers very high resolution with modest baseband and shaped noise.

Key specs — Resolution/ENOB, INL/DNL, glitch impulse (major-carry spikes), settling time (to 0.5-LSB), SFDR/SNR/THD, reference type/drive, output compliance (voltage/current).
Typical circuits — voltage-output DAC + buffer (op-amp GBW & slew sized for step settling); current-output DAC + TIA; ΔΣ audio DAC + RC/active low-pass reconstruction.
Reconstruction filter — suppress images at k·f_u ± f_BB (f_u=update/clock). Target stopband so residual sits well below the system noise/distortion floor.

Designing for 0.5-LSB settling (sets usable update rate)

For an n-bit step, the allowed fractional error is ϵ ≈ 0.5/2ⁿ. With a single-pole closed-loop response, the required time constant is τ ≤ t_settle / ln(1/ϵ), and the closed-loop bandwidth f_CL ≈ 1/(2π·τ).

Example: 16-bit, full-scale step, t_settle=2 µs ⇒ ϵ≈7.6e-6, ln(1/ϵ)≈11.8 ⇒ τ≤170 ns ⇒ f_CL≈0.94 MHz.
Op-amp GBW: for closed-loop gain A_CL, require GBW ≳ k·A_CL·f_CL (k≈8–12 to allow phase margin and higher-order effects).
Slew rate: ensure SR ≳ ΔV / t_slew and SR ≳ 2π·f_max·V_pk. If slew-limited, the small-signal settling math above no longer applies—raise SR or reduce step amplitude per update.

Reconstruction filter · tie it to the update rate

A zero-order hold (ZOH) shapes the spectrum by H(f)=T_u·sinc(πfT_u)·e^−jπfT_u; images appear near k·f_u. Choose filter order/cutoff so the first image at f≈f_u−f_BB is below the target SFDR/SNR budget.

Worked case: f_BB=20 kHz, f_u=200 ksps ⇒ first image ≈ 180 kHz. If SFDR target is 90 dBc and the raw image is −20 to −30 dB down from ZOH alone, the reconstruction LPF must add ≥60–70 dB attenuation by ~180 kHz.
Filter choices: Bessel/low-order for time-domain fidelity; Butterworth/Chebyshev or active multi-pole for stringent stopband. Verify passband droop from the ZOH sinc envelope.

Glitch impulse · quantify and mitigate

What it is: bit transitions (especially major carry) inject a short-duration impulse (specified in nV·s or pV·s). Wideband by nature, it raises out-of-band energy and can leak back in via nonlinearities.
Architectural fixes: segmented/thermometer coding, return-to-zero latching, matched timing; current-steering DACs often specify lower glitch for wideband uses.
Filter/buffer fixes: a first-order LPF with time constant τ sees a peak on the order of Q/τ (Q=glitch area). Lower Q (pick better DAC), or raise τ (more filtering) or add output capacitance where stability allows.

Current-output DAC with TIA · stability and bandwidth

Set full-scale: V_FS = I_FS·R_f. Ensure the op-amp output swing comfortably covers ±V_FS with margin.
Dominant pole: f_p ≈ 1/(2π·R_f·C_DAC+par). Add C_f across R_f to place a zero near the op-amp’s input pole and stabilize the TIA (start with C_f≈C_DAC+par and tune).
GBW target: GBW ≳ k·(1+R_f/R_source)·2π·f_BB, k≈10–20. Validate phase margin with the chosen C_f and layout parasitics.

Voltage-output DAC + buffer · quick rules

Pick an op-amp with GBW and SR that meet your 0.5-LSB settling at the intended step size and load.
Keep output network simple: small series-R (5–22 Ω) + C to ground for HF peaking as needed; verify stability with capacitive loads.
If you must drive long cables or multiplexed loads, consider a dedicated line driver after the reconstruction filter.

Reference & layout checklist

Low-noise, low-impedance V_ref; Kelvin route reference and ground; isolate from digital returns; decouple close to pins (multi-cap spread).
Short, symmetric DAC output routing; star-point or split analog/digital ground only where return paths are controlled.
Clock/logic edges away from the output node; align latch timing to minimize dynamic nonlinearity and glitch.

Worked example · 16-bit, 0–5 V, audio-band shaping

Goal: 0–5 V, 16-bit ENOB≈15-bit in 20 kHz baseband, update f_u=200 ksps, SFDR ≥ 90 dBc.
LSB=5/65536≈76.3 µV; 0.5-LSB≈38 µV. For t_settle=2 µs ⇒ f_CL≈0.94 MHz ⇒ GBW≈8–12×A_CL·f_CL (A_CL=1) ⇒ pick GBW≥10 MHz, SR≥2π·20 kHz·2.5 V≈0.314 V/µs (plus step margin; choose ≥5–10 V/µs).
Reconstruction LPF: first image ≈180 kHz ⇒ need ≥60–70 dB attenuation by 180 kHz. Use a 3–4-pole active LPF (e.g., 3-pole Butterworth at ~40–50 kHz); check ZOH droop across 20 kHz and equalize if necessary.
Glitch: if Q=50 nV·s, with τ=2 µs, a first-order estimate gives peak ~Q/τ≈25 µV—below 0.5-LSB; multi-bit transitions still need verification on scope.

Voltage-output DAC with op-amp buffer and reconstruction low-pass filter — Voltage-output DAC → op-amp buffer (GBW/SR sized for 0.5-LSB settling) → multi-pole low-pass for image suppression.

ENOB, INL/DNL, glitch impulse, settling time, SFDR highlights for DAC selection — Spec card: ENOB, INL/DNL, glitch impulse, settling time, SFDR—tie them to update rate and filter order.

DAC with 10 MHz Clock/Input

At 10 MHz update rates, usable performance is set by clock jitter, glitch energy, and output settling—not datasheet bits alone. Start from the highest output tone you need and back-solve limits on the clock, reconstruction filter, buffer, and layout.

Jitter ceiling — SNR_jitter ≈ -20·log10(2π·f_out,max·σ_j). Keep SNR_jitter at least 6–12 dB above the total noise floor (so it’s not the dominant limit).
Filter planning — a ZOH creates images near k·f_u. For 12–14-bit class baseband, target ≥60 dB attenuation at the first image; for 16-bit class, ≥80 dB. Choose f_c ≈ 0.3–0.45·f_u and verify passband droop vs the ZOH sinc.
Architecture — prefer segmented/current-steering DACs for 10 MHz-class updates (lower glitch, high SFDR). ΔΣ DACs can have high nominal resolution but effective bandwidth is set by their digital filter.
Buffer & load — the output stage must not be slew-limited for your step size; its closed-loop bandwidth must support settling within one update period (100 ns) or your chosen fraction of it.
Clock/data integrity — distribute the DAC clock and SYSREF/FRAME (if any) with low deterministic jitter; route high-speed lines differentially with controlled returns.

Back-solving the jitter budget

Given a required highest tone f_out,max and a target SNR_target, solve σ_j ≤ 10^−SNR/20 / (2π·f_out,max).

Example A: f_out,max=1 MHz, SNR_target=92 dB ⇒ σ_j≤~160 fs RMS.
Example B: f_out,max=3 MHz, same SNR ⇒ σ_j≤~53 fs RMS. Jitter dominates quickly with higher output tones.
Budget clock source, distribution, and DAC aperture together; keep deterministic jitter (DCD, ISI) small vs random jitter.

Reconstruction filter · tie stopband to the first image

With f_u=10 MHz and baseband f_BB, the first image sits near f≈f_u−f_BB. Combine ZOH sinc roll-off with a multi-pole low-pass so the image is below the distortion/noise budget.

Worked target: f_BB=1 MHz tone, f_u=10 MHz ⇒ first image ≈ 9 MHz. For 16-bit-class results, plan ≥80 dB attenuation at 9 MHz with f_c≈3–4 MHz (verify passband droop across 1 MHz).
Filter choices: 3–5 pole active LPF (Butterworth/Chebyshev) or RF LC networks; ensure op-amp stability with expected capacitive load.

Settling within a 100 ns update

For an n-bit step, allowed fractional error is ϵ≈0.5/2ⁿ. With a single-pole response, τ≤t_settle/ln(1/ϵ) and f_CL≈1/(2π·τ).

Example: 14-bit full-scale step, allow t_settle=60 ns (within the 100 ns period). ϵ≈3.05e−5 ⇒ ln(1/ϵ)≈10.4 ⇒ τ≤5.8 ns ⇒ f_CL≈27 MHz.
Op-amp needs: GBW ≳ k·A_CL·f_CL with k≈8–12; SR must exceed both step slew (ΔV/ t_slew) and sine-slew (2πf_BBV_pk).
If the chain is slew-limited, reduce ΔV per update (dithered multi-step), or move to RF-stable drivers/buffers or transformer/LC loads.

Choose the DAC architecture · manage glitch

Segmented/current-steering: high update rate, good SFDR, low major-carry glitch with thermometer segmentation and timing alignment.
Glitch estimate: a first-order LPF (τ) sees a peak on the order of Q/τ (Q = glitch area). Lower Q (better DAC), raise τ (more filtering), or add small C at the output if stability allows.
ΔΣ DACs: excellent baseband linearity/noise, but effective bandwidth is bounded by their digital filter; 10 MHz clocks do not imply 10 MHz updates.

Clock, layout & timing checklist

Differential clock and data with controlled impedance; minimize skew between data and latch/clock; isolate returns to avoid shared inductance.
Keep digital edges and switching supplies away from the analog output plane; star or well-planned split grounds; decouple close to pins with multi-cap spread.
Verify deterministic jitter (DCD/ISI) and PLL spur coupling; budget them as part of SNR_jitter.

Worked target · 10 MHz updates, 1 MHz tone, 16-bit-class

Clock/jitter: SNR_target=92 dB at 1 MHz ⇒ σ_j≤~160 fs RMS including source + distribution + DAC aperture.
Filter: f_c≈3–4 MHz; ≥80 dB at 9 MHz (first image). Account for ZOH droop over 1 MHz baseband; equalize if needed.
Buffer: closed-loop f_CL≥25–30 MHz; GBW≥(8–12)·A_CL·f_CL; SR sized for intended amplitude without slew limiting.
DAC: segmented/current-steering with low glitch impulse and SFDR≥90 dBc at 1 MHz; verify on-board timing (latch, output enable) at 10 MHz updates.

Jitter-limited SNR and update-rate budget for a 10 MHz DAC — Jitter budget: SNR_jitter ≈ −20·log10(2π·f_out,max·σ_j). Example: 1 MHz at 92 dB ⇒ ~160 fs RMS.

Reconstruction filter with stopband at the first image for 10 MHz DAC updates — Reconstruction LPF targeting ≥80 dB at the first image (≈9 MHz for 1 MHz baseband at 10 MHz update).

IC Selection & Second Source — analog to digital converter IC / chip

Send your specs or BOM and receive three pin-compatible options within 48 hours—each with indicative lead-time and price ranges, plus V_ref/driver/layout guidance. We work daily with small-batch buyers (prototyping & pilot runs) and can source across TI, ADI, Microchip, Renesas, NXP, onsemi, ST and more. If you need an analog to digital converter IC fast—or a safe second source—we’ve got you.

Get 3 options in 48h

Small-batch friendly · Pin-compatible first · Lead-time & price bands included

To match quickly, include:

Sampling rate / bandwidth (f_s, BW), target resolution / ENOB
Channels & sync (simultaneous / multiplexed), input type & range (SE/diff)
Interface need (SPI / LVDS / JESD204 / parallel), clocking constraints
Package / pinout / supply rails, board constraints (footprint/height)
Standards & environment (RoHS/REACH, AEC-Q, temp range, isolation)

(Optional) Use our one-page spec checklist

Representative families (scan & shortlist)

Texas Instruments

Precision ΔΣ: ADS127Lxx / ADS126x — 24-bit ≤512 kSPS · SPI · metering/DAQ
General SAR: ADS888x / ADS868x — 16–18-bit ≤1–2 MSPS · SPI/parallel
High-speed: ADC12J/ADC32J — JESD, 100 MSPS–GSPS

Lead-time (indicative): 2–4w / 6–10w depending on family.

Analog Devices

Precision ΔΣ: AD7768 / AD717x — 24-bit multi-ch · SPI
General SAR: AD798x / AD400x — 16–18-bit ≤2 MSPS · SPI
High-speed: AD96xx / AD92xx — 12–16-bit ≥100 MSPS · LVDS/JESD

Lead-time (indicative): 3–6w+; samples often faster.

Microchip

Precision ΔΣ: MCP356x — 24-bit ≤153 kSPS · SPI
General SAR: MCP331x / MCP320x — 12–16-bit ≤1 MSPS · SPI
High-speed: MCP37Dxx — 16-bit tens–hundreds MSPS · LVDS/parallel

Lead-time (indicative): 2–8w by package/variant.

Renesas

Precision ΔΣ: ISL261xx — 24-bit low-speed high-accuracy
High-speed: ISLA1xx/2xx — 12–14-bit, tens–hundreds MSPS · LVDS
SAR: select RA/ISL external SAR lines · SPI

Lead-time (indicative): 3–8w; automotive may vary.

NXP

Integrated focus: i.MX/RT/MCU with 12–16-bit SAR on-chip
External strategy: we cross-brand to matching external ADCs

Use case driven; we shortlist by interface & ENOB.

onsemi

High-speed: KAD55xx/KAD27xx — 12–16-bit 50–250 MSPS
Imaging/ToF: AFE + ADC signal-chain pairings

Great for vision/TOF; we map drop-in alternates if needed.

STMicroelectronics

Integrated focus: STM32 families with on-chip SAR
External pairing: combine with ADI/TI/Microchip for higher ENOB/rate/interface

We align package & pinouts to reduce rework.

Small-batch friendly

MOQ tiers: 10 / 25 / 50 / 100 units
Mix-and-match within families (same footprint)
Sample orders with priority handling

When you must replace

NRND/EOL risk or repeated shortages
Pin-to-pin upgrade (ENOB / rate / interface)
Compliance/temperature/isolation step-up

What you’ll receive in 48h

3 short-listed, pin-compatible analog to digital converter chips with indicative lead-time & price bands
Vref/Driver suggestions and layout notes (RC/decoupling/grounding)
Optional side-by-side comparison (performance/power/cost/interface/risks)

RoHS/REACH compliant · Optional AEC-Q · Traceable lots with COC · NDA on request · Standard warranty

View chapter

Submit RFQ / Get 3 options

We reply within 48 hours on business days.

Need help sizing drivers or interfaces? See Front-End & Vref, Interfaces, and Resolution / ENOB / SNR.

Catalog preview of analog to digital converter chips across major brands — Quick scan of ADC families; final shortlist is tailored to your specs, footprint and timeline.

FAQ · Knowledge

Each answer is 40–60 words. Open a box to read. Buttons: “Read more” and “Get IC Picks (48h)”.

What is an ADC?

An ADC samples an analog voltage or current and outputs an n-bit code referenced to Vref. The core steps are sample, hold, quantize, and encode. ADCs let digital systems measure real-world signals for control, logging, and communications. Typical inputs are sensor voltages or currents produced by transducers.

How does an ADC work?

A sample-and-hold captures the input; the core (SAR/ΔΣ/pipeline/flash) compares it to a reference to choose a code; logic formats and outputs data via SPI/LVDS/JESD. Driver settling, reference noise, and clocking largely determine accuracy and latency, especially at higher input frequencies.

What are ADC types?

SAR favors low latency and moderate-to-high speed with simple drivers. ΔΣ delivers high resolution and mains-hum rejection at the cost of latency. Pipeline spans multi-MSPS to GSPS, while flash is ultra-fast but power-hungry. Choose by bandwidth, resolution, latency, and driver complexity.

What is ADC resolution / ENOB?

Resolution is nominal bit depth; ENOB is effective bits under noise. They relate via ENOB ≈ (SNR − 1.76) / 6.02. Translate required dynamic range into bits and LSB size, then verify ENOB at your actual rate, bandwidth, reference quality, and jitter to avoid optimistic assumptions.

What causes INL/DNL & missing codes?

DNL measures step-width error; INL is cumulative deviation from the ideal line. DNL < −1 LSB risks missing codes or non-monotonic behavior. Diagnose with ramp or code-density tests, then fix driver settling, reference noise, and timing—or select a converter specified for tighter linearity.

How to convert analog to digital correctly?

Limit bandwidth with an anti-alias filter, sample at ≥2× signal bandwidth, choose an architecture that fits resolution and latency, budget reference/driver noise, then calibrate gain, offset and temperature. For SAR, size the input RC to meet ≈0.5-LSB settling within the acquisition window.

Do I need an external ADC if my MCU has one?

Use an MCU ADC for general sensing. Go external at ≥16-bit targets, ≥2 MSPS per channel, multi-channel sync, isolation or deterministic latency needs. External SAR/ΔΣ/pipeline/flash can also improve linearity, noise and interface options (LVDS/JESD204).

Which interface should I use?

Estimate bandwidth with throughput = f_s × bits × channels / efficiency. SPI suits low/medium rates; LVDS scales with DDR pairs; JESD204 (B/C) handles multi-Gb/s and deterministic latency. Plan lane count, alignment and clock quality before layout to avoid late-stage rework.

Which ADC IC should I pick?

Send a brief spec or BOM and we’ll shortlist three pin-compatible options with lead-time and price ranges inside 48 hours—plus Vref/driver/layout guidance across TI, ADI, Microchip, Renesas, NXP, onsemi and ST. Small-batch friendly.

How do I add an ADC to a Raspberry Pi?

Use an external converter over SPI (MCP3008/3208, AD400x) or I²C (ADS1115). Keep source impedance low, add a small series-R + shunt-C at the ADC pin (SAR) to tame S/H kickback, and power the reference cleanly. SPI with DMA enables higher continuous rates; I²C is simpler but slower. See Raspberry Pi · Adding an External ADC.

What is a good digital to analog converter circuit?

Match the DAC architecture to bandwidth and linearity, then size the buffer and reconstruction filter so 0.5-LSB settling, SFDR and glitch impulse are met at the update rate. Voltage-output DACs need GBW/SR for steps; current-output DACs need a stable TIA (Rf/Cf). Keep V_ref quiet and Kelvin-routed. See DAC Basics · Circuits & Specs.

Digital to analog converter with a 10 MHz clock—what matters?

Back-solve jitter so SNR_jitter clears your noise floor, place the reconstruction cutoff so the first image is ≥60–80 dB down, and ensure the buffer is not slew-limited and settles within the 100 ns update. Prefer segmented/current-steering DACs, control skew and returns, and verify SFDR at the target tone. See DAC with 10 MHz Clock/Input.