ADC Interfaces: SPI vs LVDS vs JESD204

Which ADC Interface Should I Use? SPI vs LVDS vs JESD204

Got fs, bits, channels, your host (MCU/FPGA), and need deterministic latency? Use the flow below to pick the right ADC interface.

SPI — Simple and MCU-friendly; up to tens of Mbps; best for few channels / lower rates.
LVDS — Mid-to-high speed, differential and source-synchronous; common on fast SAR/pipeline ADCs.
JESD204 (B/C) — Very high throughput, multi-channel, deterministic latency, scalable; requires FPGA/SerDes.

Skip the theory — go to the quick picker ↓

A wordless 3:2 diagram comparing SPI, LVDS, and JESD204 for ADC interfaces by throughput, complexity, and scalability.

Want to learn What is an ADC? Read the definition →

Quick Picker — Decision Flow & One-Line Math

Have answers to four quick questions? Follow them to a safe interface choice.

Q1 — Is total throughput fs × bits × channels > ~30–50 Mbps?

Yes · go Q2 (skip SPI) No · keep SPI (go Q2)

Q2 — Do you need deterministic latency or multi-device sync?

Yes · prefer JESD204 No · go Q3

(JESD204 uses SYSREF and multi-lane alignment for deterministic latency.)

Q3 — Is your host only an MCU (no FPGA/SerDes)?

Yes · prefer SPI No · go Q4

Q4 — Is routing long or the environment noisy/EMI-heavy?

Yes · prefer LVDS/JESD No · SPI may work

Required bit rate ≈ (fs × bits × channels) / E_coding

SPI ≈ 1.00 8b/10b ≈ 0.80 64b/66b ≈ 0.97

Leave 10–20% headroom for framing/alignment/headers.

Example — 2ch × 14-bit × 5 MS/s ⇒ 140 Mbps raw; with 8b/10b ≈ 175 Mbps; +20% headroom ⇒ ≈ 210 Mbps → LVDS turf.

Outcome: SPI candidate — jump to SPI tips ↓

Outcome: LVDS recommended — jump to LVDS tips ↓

Outcome: Consider JESD204 (B/C) — jump to JESD tips ↓

SPI: Watch MCU SCLK ceiling and DMA; long or cross-board wires are risky.
LVDS: Keep 100 Ω differential impedance, length match, and place termination correctly.
JESD204: Calculate lane rate × lane count; Subclass/SYSREF drive determinism.

SPI — When to Use, Limits, Layout & Bring-up

A wordless diagram showing an MCU connected to an ADC over SPI with short traces, source series resistors, and a clear clock return path.

3.1 When SPI makes sense

Low / mid-speed capture, single or few channels; direct MCU connection.
Prototype / small-batch builds need a fast bring-up with low BOM and tooling cost.
Lightweight integration with firmware/GUI, no FPGA/SerDes required.

3.2 Throughput limits & safe margin

Quick estimate (SPI uses E_coding ≈ 1.00):
Required SCLK ≈ (fs × bits × channels) / E_coding

Leave 10–20% headroom for framing, alignment and device wait states.
Typical MCU sustainable SCLK spans ~10–40 MHz (higher is possible but board routing, load and DMA overhead apply).
Long runs / cross-board jumpers / noisy environments lower the practical SCLK ceiling.

Example: 16-bit × 1 ch × 500 kS/s → 8 Mbps raw; +20% headroom → ≈9.6 Mbps SCLK ⇒ SPI is feasible on many MCUs if routing is short and clean.

3.3 Layout — Do

Keep traces short, continuous reference plane; ensure a clear clock return path.
Place 22–47 Ω source series resistors on SCLK/MOSI near the driver to tame ringing/overshoot.
Use proper near-receiver termination/mode per datasheet (pull-ups/downs, Schmitt options).
Isolate from switchers/motors; if you split grounds, single-point tie near the ADC.

3.3 Layout — Don’t

No long breadboard leads or ribbon cables for high-edge SCLK.
Avoid casual level shifters between 1.8↔3.3 V — they add skew and edge distortion.
Don’t meander CS/DRDY — sloppy routing eats setup/hold margins.

3.4 Bring-up checklist (step-by-step)

Power & reference: verify Vref decoupling and ground bounce (scope the ripple).
Probe the link at low SCLK: read the fixed device ID/version register first.
Match SPI mode: set CPOL/CPHA per datasheet; confirm bit order (MSB/LSB).
Code format sanity: apply a static step input and check Straight / Offset-Binary / Two’s-Complement decoding.
Edge timing margin: raise SCLK gradually; measure MISO sampling window (LA/scope).
DMA / ISR: enable circular DMA or double buffer; watch for overrun / dropped samples.
Integrity checks: enable frame header/CRC/alignment flags if supported.
Soak test: run 10–30 min under thermal/load variation; track code jitter and error counters.

3.5 Common pitfalls (symptom → fix)

Waveform looks fine but codes are wrong: CPOL/CPHA or bit order mismatched to the timing diagram.
Sporadic misalignment / lost codes: CS/DRDY setup/hold violated; SCLK edge too sharp → add series resistors.
Random codes after long/cross-board runs: poor edge integrity → buffer, series damping, or move to differential.
I/O domain mismatch: ADC and MCU voltage levels differ → use a proper same-domain pairing or a spec’d translator.

3.6 When NOT to use SPI

When fs × bits × channels approaches or exceeds your MCU’s sustainable SCLK (incl. DMA overhead and 10–20% headroom).
When you need deterministic latency or multi-device sync (→ prefer JESD204).
When routing is long or EMI is heavy and you can’t guarantee edge integrity (→ prefer differential LVDS/JESD).

Consider LVDS ↓ Consider JESD204 ↓

LVDS — Differential, Source-Synchronous, Mid-to-High Speed

A wordless diagram of an ADC forwarding a differential clock and multiple LVDS data pairs to an FPGA with receiver-side termination and matched pairs.

4.1 When LVDS fits

Tens to hundreds of Mbps per pair; parallel data pairs (often DDR) for aggregate throughput.
Differential noise immunity and lower emissions; better for longer on-board runs or noisy environments.
Source-synchronous capture (forwarded DCO + DATAx) is friendlier than MCU-sampled SPI at these rates.

4.2 System shape

ADC forwards a differential clock (DCO+/−) plus one or more DATA+/− pairs (often DDR). The receiver (FPGA or dedicated LVDS RX) performs bit/word alignment per channel, then buffers to FIFO/processing. No heavy line coding (usually no 8b/10b), but frame/word markers may exist.

4.3 Throughput & lane math (one-liners)

T_raw = fs × bits × channels
lane_rate ≈ T_raw / N_pairs (LVDS coding efficiency ≈ 1.00)
For DDR data: f_DCO ≈ lane_rate / 2
Unit interval: UI = 1 / lane_rate; keep intra-pair skew ≲ 10–20% UI.
If the ADC uses a serializer factor S (e.g., 7:1/14:1), compute N_pairs and f_DCO per the datasheet mapping.

4.4 Layout — Do

Route 100 Ω differential pairs, tightly matched length; control intra-pair skew within your UI budget.
Maintain a continuous reference plane; pre-plan return paths when crossing layers or plane splits.
Place termination at the receiver (or enable internal 100 Ω) close to pins.
Use paired vias, minimize stubs (back-drill/blind-buried if needed).

4.4 Layout — Don’t

No test pads/fly-wires inside a pair — they create stubs.
Avoid crossing plane splits or running parallel to noisy switching rails.
Don’t mismatch pair lengths or swap P/N; both collapse eye opening.

4.5 Bring-up checklist

Lock DCO & data: verify DCO frequency/duty and DDR relationship to DATAx (scope/LA/ILA).
Frame/word alignment: enable the device’s align mode or implement bit-slip/word-align in the FPGA.
Lane matching: align channels (bit/word) and measure lane-to-lane skew.
Jitter margin: check sampling edge margin; tune input delay/phase on the FPGA; reduce on-board noise sources if needed.
Integrity checks: run known patterns (fixed/step codes) and track error/lost-frame indicators.
Soak test: 10–30 min over temp/load; ensure no intermittent misalignment.

4.6 Common pitfalls

P/N swaps or pair crossovers → inverted/garbled codes.
No/incorrect termination or wrong location → amplitude issues, crosstalk/EMI rise.
Excessive intra-pair or lane-to-lane skew → collapsed eye, random bit errors.
Poor DCO duty/jitter → reduced sampling window, intermittent faults.

4.7 When to step up to JESD204

More channels or rising aggregate throughput demanding scalability.
Off-board/cable links or deterministic latency and system-wide synchronization.
Planned lane aggregation or distributed acquisition architectures.

Go to JESD204 ↓

JESD204 (B/C) — Ultra-High Throughput, Multi-Channel, Deterministic

A wordless diagram of a multi-lane JESD204 link from an ADC to an FPGA, showing CGS→ILAS→DATA stages with SYSREF/LMFC timing cues.

5.1 When JESD204 makes sense

Very high aggregate throughput and/or many channels beyond LVDS comfort.
Deterministic latency and fleet-wide synchronization needs (Subclass with SYSREF/LMFC).
Scalable multi-lane SerDes links; typical host is an FPGA/SoC with SerDes.

5.2 Concepts at a glance

Multi-lane SerDes aggregates throughput; trade lane rate vs lane count.
Link bring-up stages: CGS → ILAS → DATA.
Determinism: SYSREF/LMFC (Subclass) for fixed, repeatable latency and device alignment.
Coding efficiency: 8b/10b ≈ 0.80; 64b/66b ≈ 0.97 (JESD204C supports higher efficiencies and rates).

5.3 Lane-rate math (one-liners)

T_raw = fs × bits × channels

required_line_rate ≈ T_raw / (E_coding × N_lanes)

8b/10b ≈ 0.80 64b/66b ≈ 0.97

Add 10–20% headroom for framing/multiframe, alignment, control symbols, and jitter.

Tip — Plan lane-to-lane skew and LMFC alignment windows when choosing N_lanes.

5.4 Layout & clocking — Do

Route controlled-impedance differential pairs, matched length, continuous return paths.
Use paired vias, keep stubs minimal (back-drill where needed).
Distribute low-jitter clocks and SYSREF symmetrically; document LMFC relations.
Mind PI/SI: SerDes rail decoupling, plane integrity, isolation from RF/analog front-ends.
Simulate eye/channel if possible (CTLE/DFE/pre-emphasis budgeting).

5.4 Layout & clocking — Don’t

Don’t cross plane splits or run near switching/high-current paths.
Don’t treat SYSREF as a casual GPIO; asymmetry kills determinism.
Don’t place test pads near SerDes pins; avoid return-via omissions.

5.5 Bring-up checklist (CGS → ILAS → DATA)

Clock & SYSREF up: verify ref-clock jitter, SYSREF edges, and LMFC phase relations.
CGS: achieve code-group sync; confirm character alignment stability.
ILAS: exchange parameters; match lane IDs, octets, scrambling, subclass.
DATA: enable lane alignment/deskew; align all lanes to the same LMFC.
Determinism: measure end-to-end latency; confirm cross-reset repeatability.
Error monitors: track bit/frame/multiframe errors; stress temp and supply noise.

5.6 Common pitfalls

SYSREF/LMFC mis-config or asymmetric routing → no determinism or drift across resets.
Mismatched coding/mapping (8b/10b vs 64b/66b, scrambling, F/K characters) → CGS/ILAS loops.
Excessive lane skew → lanes won’t align; intermittent bit errors.
Poor PI/SI → eye closure, rising BER; SerDes rail ripple causes wander.

5.7 When NOT to use JESD204

Your host is MCU-only (no SerDes/FPGA capability).
Aggregate throughput and channel count are modest (SPI/LVDS suffice).
Strict cost/power budgets rule out SerDes and clock-tree complexity.

Back to Quick Picker ↑ Consider LVDS ↓

Practical Patterns — From Requirements to Interface

A wordless three-panel diagram showing SPI, LVDS, and JESD204 data paths for the three example builds.

6.1 Example A — MCU + 1 ch 16-bit @ 500 kS/s → SPI

Given — 1 channel, 16-bit, fs = 500 kS/s; host = MCU; short on-board routing.

Quick math — T_raw = fs × bits × ch = 0.5e6 × 16 × 1 = 8 Mb/s. SPI E_coding ≈ 1.00 ⇒ Required SCLK ≈ 8 MHz. Add 20% headroom ⇒ ≈ 9.6 MHz.

Decision — SPI fits: many MCUs supply 20–40 MHz SCLK. If runs get long/noisy or edges are hard to tame, reassess LVDS.

Layout must-haves

Short traces + continuous reference plane; clear clock return path.
22–47 Ω source series resistors on SCLK/MOSI near the driver.
Clean CS/DRDY routing; avoid meanders that eat timing margin.

Bring-up first

Low-SCLK read device ID → confirm link.
Set CPOL/CPHA and bit order per datasheet.
Static step input to verify Straight/Offset/Two’s-Comp; raise SCLK; enable DMA.

Watch-outs

Breadboard/ribbon wiring distorts edges.
Level translators add skew and edge distortion.

Learn SPI tips ↓

6.2 Example B — FPGA + 2 ch 14-bit @ 5 MS/s → LVDS

Given — 2 channels, 14-bit, fs = 5 MS/s; host = FPGA/LVDS RX; prefers longer runs and better noise immunity.

Quick math — T_raw = 2 × 14 × 5e6 = 140 Mb/s. Choose 2 DATA pairs + 1 DCO pair: lane_rate ≈ 140 / 2 = 70 Mb/s. DDR ⇒ f_DCO ≈ 70/2 = 35 MHz. Add 20% headroom ⇒ ≈ 84 Mb/s per pair.

Decision — LVDS fits: comfortable tens-of-Mb/s per pair; differential + source-sync is friendlier than MCU-sampled SPI here.

Layout must-haves

100 Ω differential, tight intra-pair match; receiver-side termination near pins.
Continuous reference plane; plan returns across layer/plane changes; paired vias; minimize stubs.

Bring-up first

Lock DCO frequency/duty and DDR relation to DATAx; enable bit/word-align.
Calibrate lane-to-lane skew; run fixed/step patterns and check error counters.

Watch-outs

P/N swaps, missing termination, excessive intra-pair skew → eye collapse/random errors.

Learn LVDS tips ↓

6.3 Example C — FPGA + 8 ch 14-bit @ 125 MS/s → JESD204 (B/C)

Given — 8 channels, 14-bit, fs = 125 MS/s; needs scalability and deterministic latency; host = FPGA/SerDes.

Quick math — T_raw = 8 × 14 × 125e6 = 14,000 Mb/s = 14 Gb/s.

JESD204B (8b/10b, E ≈ 0.80):
4 lanes → 14 / (0.80 × 4) = 4.375 Gb/s per lane; +20% ⇒ ≈ 5.25 Gb/s
8 lanes → 14 / (0.80 × 8) = 2.1875 Gb/s per lane; +20% ⇒ ≈ 2.63 Gb/s
JESD204C (64b/66b, E ≈ 0.97):
4 lanes → 14 / (0.97 × 4) = 3.61 Gb/s per lane; +20% ⇒ ≈ 4.33 Gb/s
8 lanes → 14 / (0.97 × 8) = 1.80 Gb/s per lane; +20% ⇒ ≈ 2.16 Gb/s

Decision — JESD204 is the right class. Choose lane count and coding per ADC/FPGA limits: B (8b/10b) may need more lanes at high rates; C (64b/66b) achieves the same throughput with fewer lanes or lower line rates. Use Subclass + SYSREF/LMFC for determinism.

Layout must-haves

Strict SerDes pair impedance/length/return control; paired vias; minimal stubs (back-drill if needed).
Low-jitter clocks and SYSREF distributed symmetrically; solid PI/SI for SerDes rails.

Bring-up first

Bring up Clock & SYSREF → pass CGS → ILAS → DATA.
Enable deskew/alignment to a common LMFC; verify deterministic latency across resets; track BER/frame/multiframe.

Watch-outs

SYSREF asymmetry or config mismatch; excessive lane skew; SerDes rail ripple → instability or lost determinism.

Learn JESD tips ↓

FAQ — Interface Selection

When does SPI stop making sense?

SPI fails when your required SCLK ≈ fs × bits × channels approaches the MCU’s sustainable clock even with 10–20% headroom. Long runs, noisy boards, or tight setup/hold also bite. If you need deterministic latency or multi-device sync, jump to LVDS or JESD204 instead. Read more →

Is LVDS always better than SPI?

No. LVDS wins for noise immunity and mid/high speed with a forwarded clock, but it adds extra pairs, termination, routing rules, and BOM. For few-channel, modest rates on an MCU, SPI is cheaper and simpler. Choose LVDS when routing is longer/noisier or throughput exceeds SPI margins. Read more →

Do I need JESD204-B or -C?

Both deliver multi-lane SerDes and deterministic latency via SYSREF/LMFC. B uses 8b/10b (≈0.80 efficiency), widely supported. C uses 64b/66b (≈0.97), enabling higher effective throughput or fewer lanes at the same load. Pick what your ADC/FPGA support and what meets lane-rate limits. Read more →

How many lanes do I need?

Start with T_raw = fs × bits × channels. Estimate lanes ≈ ceil( T_raw / ( E_coding × lane_rate_max ) ), where E_coding ≈ 0.80 (8b/10b) or 0.97 (64b/66b). Keep 10–20% headroom for framing/alignment/jitter, and ensure lane-to-lane skew fits the alignment window. Read more →