How to Convert Analog to Digital: Step-by-Step

Where to place the filter: for single-ended signals, use a series R and a shunt C to ground. If you buffer, put the RC after the buffer and before the ADC IN. For differential inputs, use symmetrical RC on both legs and maintain common-mode. Keep the capacitor’s return at a clean local ground near the ADC (avoid split-plane crossings).

Mind the ADC’s sample-and-hold: too large a series R can prevent the internal sampling capacitor from charging within the aperture/hold window.

• Relying on digital filtering to fix aliasing—once folded, it cannot be undone.
• Putting the RC at a far location (edge of the board/probe side), letting the trace pick up new noise and spikes.
• Choosing an overly large series R so the S/H capacitor never fully charges; or using the wrong capacitor dielectric for stability.

• Sweep a sine toward f_s/2 and compare spectra: with vs without RC, alias peaks should drop clearly.
• Feed a square/pulse and observe edge rounding; if high-frequency “texture” remains in codes, reduce f_c (e.g., 0.3×f_s) or go 2nd-order.
• Re-check the S/H charge time constant vs your sampling aperture/hold; adjust series R or add a buffer.

• Low–mid speed, general accuracy → choose SAR. (Often built into MCUs; simple, low latency.)
• High dynamic range / audio-grade linearity → choose ΔΣ. (Oversampling + digital filtering; tolerate latency.)
• High bandwidth, ultra-low latency → choose Pipeline/Flash. (Higher power/cost; FPGA-friendly interfaces.)

• Is your priority dynamic range/linearity or bandwidth/latency?
• What latency can the system tolerate (ms vs µs)?
• Can the front-end drive the chosen ADC (low source impedance, adequate GBW)?
• Do target bits align with realistic ENOB/SNR given Vref and noise budget?

Make sure energy actually arrives: the source + R_series and the ADC’s internal S/H capacitor form a time constant. It should settle within the sampling aperture to well below a fraction of an LSB—higher source impedance demands a stronger driver and/or smaller R_series.

Common-mode & input window: confirm polarity (unipolar/bipolar) and the allowed common-mode range. Apply bias/shift after the buffer so that the instantaneous sampling voltage always stays in range.

Stability: the driver + RC can ring; slightly increase R_series or add a small output cap (pF-level) if you see overshoot.

• Clamp & limit: R_series + diodes to AVDD/AGND (or Schottky to a reference rail) to absorb transients/over-voltage.
• EMI/ESD: consider TVS / RC snubbers at the connector; keep return loops tight near the ADC analog ground.
• Layout: shortest path from RC to ADC pin; capacitor returns to a clean local ground (avoid split-plane crossings).

• High source impedance driving a fast SAR → S/H never fully charges; distortion and INL/THD degrade.
• No input protection → probe/plug transients punch the ADC pin beyond rails.
• Common-mode out of range (VOCM mis-set on differential inputs) → codes look “valid” but are biased or clipped.

• Before power-on: VOCM, supply rails, and input window verified? RC located right at the driver/ADC with a clean local ground return?
• Step test: feed a small step/square; watch for under-settling or ringing in codes—reduce R_series, increase driver GBW, or move to a 2nd-order RC if needed.
• Sine sweep: raise frequency/amplitude; check for clipping and rising THD—if present, revisit source impedance and bias window.

Supply & topology:

• MCU internal ADC: start with the internal reference; upgrade to an external 2.5 V/4.096 V reference if noise/linearity demand it. Still place 10 µF ∥ 0.1 µF near Vref/Vdda.
• External ADC: reference IC → (optional small R/FB bead if allowed) → Vref pin. Use differential reference where supported for better PSRR.

Placement & parts: 0.1 µF = C0G/NP0; 10 µF = X7R. Keep caps adjacent to the pin, same layer, with a tight return to AGND. Keep references away from hot/noisy switchers and clocks.

• Ripple at Vref pin: < 10 mV_pp as a minimum bar for 12-bit designs (tighten for higher resolution).
• Startup: wait for the reference to settle (datasheet ms-scale) before calibration/measurement.
• Code histogram: with a static input, distribution should be tight with no odd missing-code gaps.

• Sharing USB/digital rails for Vref — ripple and spikes map straight into LSBs.
• Decouplers placed far away or returning across split planes — large loop inductance → jitter and coupling.
• Ground bounce from digital high-current paths contaminating the analog reference loop.

• Are 10 µF ∥ 0.1 µF on the same layer right next to Vref, with a short return to AGND?
• Is Vref sourced from a clean LDO/reference (not a noisy digital rail), and tied to DGND only at a single point?
• Scope the Vref pin: ripple < 10 mV_pp? No switching texture? If not, fix supply/placement before chasing higher ENOB.

Jitter-limited SNR follows SNR_jitter ≈ −20·log₁₀(2π·f_in·σ_t). Use these total RMS jitter targets to roughly preserve ENOB:

• At 100 kHz input: 12-bit ≲ 320 ps, 14-bit ≲ 80 ps, 16-bit ≲ 20 ps.
• At 1 MHz input: 12-bit ≲ 32 ps, 14-bit ≲ 8 ps, 16-bit ≲ 2 ps.

Total jitter = √(source² + distribution/buffer² + ADC aperture²). Fix the source first.

• Assuming digital filtering can recover jitter loss — it cannot; jitter corrupts the sampling instant.
• Using an MCU PLL as the primary sample clock without dedicated clean power/decoupling.
• Clock traces that cross split planes or meander near Vref/analog paths, increasing phase noise and coupling.

• Before power-on: clock source on a clean LDO with local 10 µF ∥ 0.1 µF? Traces short, no plane crossings, proper terminations?
• After power-on (sine sweep): increase f_in; if SNR drops earlier than expected, swap to a lower-jitter XO/module and re-check.

throughput ≈ bits × channels × fs / efficiency

• bits = effective frame width per sample (include status/alignment bits if present).
• channels = simultaneous channels (account for interleaving rules).
• f_s = per-channel sampling rate.
• efficiency = protocol & framing overhead (typ. 0.6–0.95 for real sustained streaming).

Compare the result to your MCU/FPGA’s sustained link limits (SPI mode/CS gaps/DMA service time), not just headline MHz.

• Lock to the ADC’s frame header/status bits; verify channel order for interleaved streams.
• Use FIFO/DMA with a circular buffer. Size guard-band: buffer_bytes ≈ throughput (B/s) × guard_time (s).
• Prefer hardware timers to trigger conversions for stable time-base.

• Single-ended: Sensor → RC → Buffer → ADC_IN; small series R (10–100 Ω) before S/H.
• Differential (if supported): Symmetrical RC + differential driver; set common-mode per datasheet.
• Code formats:
  • Straight (natural): read as unsigned.
  • Offset-Binary: convert to signed: signed = code − 2^(N−1).
  • Two’s-Complement: ensure sign-extension and correct left/right alignment; confirm MSB-first.
• Data movement: use DMA (circular). Interrupts handle watermarks/flags only; avoid CPU polling.
• Oversampling/Averaging: reduces noise but changes data rate/bandwidth — include in throughput budgeting.

• Using headline link MHz without sustained throughput budgeting → dropped samples.
• Wrong SPI mode/edge, bit order, or alignment → shifted/unstable codes.
• Misreading code format (Offset-Binary vs Two’s-Complement) → polarity/zero offset errors.
• No FIFO/DMA → CPU stalls cause intermittent data loss, especially multi-channel.
• Multi-channel interleave channel order not verified → cross-talk misinterpretation.

• Before power-on: compute bits × channels × fs / efficiency, compare to sustained link limits, leave 20–30% headroom.
• SPI: confirm CPOL/CPHA, bit order, alignment, frame length; pre-configure DMA circular buffer.
• After power-on: logic analyzer one frame — verify header, bit order, frame length, channel order.
• Feed a ramp/step: check monotonicity and correct sign/zero; toggle oversampling to confirm expected throughput/noise change.

• DMM (for rails/offsets), oscilloscope (probe Vref ripple directly at the pin)
• Signal generator (sine & step), known reference (short/precision divider/reference IC)
• Logic analyzer (optional, to confirm frame/header/bit order)

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