Gate Driver IC: Circuit, High-Side, Isolated & Faults

Gate driver IC

A gate driver IC is an integrated circuit that converts logic-level control into high-current, fast edges to switch MOSFETs/IGBTs safely and efficiently. Use a gate driver IC whenever switching speed, voltage, isolation, or protection requirements exceed what a bare MCU/FPGA pin can provide.

Do I need a gate driver?

Switching frequency ≥ 20–50 kHz → MCU pin rise/fall too slow, switching loss increases.
Gate charge Q_g ≥ 20–50 nC or required peak gate current ≥ 0.5–2 A.
Topologies with high-side / half-bridge / full-bridge / three-phase devices.
Need isolation/CMTI robustness (harsh dv/dt, SiC/GaN/IGBT) or safety insulation.
Need protections: UVLO, DESAT/soft turn-off, Miller clamp, dead-time, diagnostics.

gate driver circuit — low-side, high-side, half-bridge, full-bridge. — Topology overview: low-side, high-side, half-bridge, full-bridge, three-phase.

Topology	Bootstrap?	Isolation typical	Typical bus	Notes
Low-side	No	Optional	12–100 V	Simplest; good for synchronous rectifiers.
High-side	Yes (common)	Often needed	24–600 V+	Bootstrap limits 100% duty; see high-side.
Half-bridge	Yes (HS)	Common	48–800 V	Dead-time & delay matching are critical.
Full-bridge	Yes (2×HS)	Common	48–800 V	Skew/propagation mismatch can cause shoot-through.
Three-phase	Yes (3×HS)	Common	200–800 V	Use matched multi-channel or isolated drivers.

Isolation essentials

Non-isolated vs isolated (magnetic/capacitive/optical) depends on safety and noise immunity.
CMTI requirement rises with SiC/GaN/fast IGBT; select drivers with high dv/dt tolerance.
When primary/secondary grounds must be broken or 100% duty is needed, consider a gate driver transformer.

Smart protections to look for

UVLO on input/driver rails for clean turn-on/off thresholds.
DESAT + soft turn-off (fast short-circuit protection; vital for IGBT/SiC).
Miller clamp, programmable dead-time, cross-conduction prevention.
Diagnostics: FAULT, EN, optional SPI telemetry.

Quick calc — drive power

P_drive ≈ Q_g · V_g · f

Example: Q_g=80 nC, V_g=10 V, f=100 kHz → P_drive≈0.08 W. (Rule of thumb: I_peak ≈ Q_g/t_r.)

Common pitfalls

Driving directly from MCU → slow edges, excess switching loss & heating.
Bootstrap high-side assumed 100% duty → see limitations.
Poor ground/reference routing → false triggering or damage; see layout tips.

What is a gate driver IC?

A small integrated circuit that sources/sinks amp-level currents to charge/discharge a power transistor’s gate quickly, often adding isolation and protections (UVLO, DESAT, Miller clamp).

Do I need a gate driver?

Yes, when frequency, Q_g, topology (high-side/bridge), isolation, or protection needs exceed simple GPIO capability. Use the checklist above to decide.

Further reading: Gate driver ICs · High-side gate driver · Isolated gate driver · Gate driver design

Reference: Wikipedia — Gate driver · MOSFET

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Gate Driver Circuit

A gate driver circuit combines the driver IC, its supply (or bootstrap/isolated power), and the gate network (Rg/Miller clamp/snubber) with a tight return path. Start by choosing the topology—low-side, high-side, half-bridge, or full-bridge—then solve supply and timing (dead-time & propagation delay matching).

Topology	Driver form	Supply method	Timing essentials	Common pitfalls
Low-side	Single-channel non-isolated	Local 10–15 V rail	Minimal skew; set Rg for EMI vs speed	Long gate loop; Miller turn-on; poor return path
High-side	High-side channel (often with LS)	Bootstrap or isolated supply	Duty-cycle windows for C_boot recharge	Assuming 100% duty; insufficient C_boot; dv/dt false turn-on
Half-bridge	Dual (HS+LS) matched channels	Bootstrap HS + local LS or isolated dual	Dead-time & delay matching between arms	Shoot-through from skew; cross-coupled ringing
Full-bridge	Two half-bridges (4 channels)	As above ×2; often isolated	Cross-leg sync; diagonal conduction prevention	Mismatch between legs; dead-time too short/long

Supply & bootstrap (quick rules)

Bootstrap needs low-side on-time to recharge. For sustained high duty or very low frequency, switch to an isolated gate driver or isolated supply.
Size the capacitor: C_boot ≥ (Q_total + Q_leak + margin) / ΔV_allow, where Q_total includes high-side Q_g and driver overhead.
Place diode, C_boot, and return as a compact loop close to the driver pins.

bootstrap duty cycle — Bootstrap supply and duty-cycle limit illustration

Dead-time & propagation delay matching

Too short → shoot-through; too long → body-diode conduction & loss.
Prefer drivers with matched channels and adjustable dead-time; verify skew over temperature.
Measure at gate-to-emitter/source (Kelvin) with a differential probe.

deadtime delay matching — Dead-time and delay matching diagram (2:1).

Gate network basics

Use split Rg (pull-up/pull-down) to balance EMI vs switching loss.
Miller clamp or small negative bias helps against dv/dt induced turn-on.
RC snubber/damping to control ringing; minimize gate loop area; prefer Kelvin source packages.

high side gate driver (bootstrap duty-cycle limits)

A high side gate driver often relies on a bootstrap diode and capacitor. At very high duty cycles, low frequency, or light load, recharge windows shrink and the high-side supply sags. Options: shorten the max duty window, add assisted charge (charge pump/aux path), or move to an isolated driver/supply. See more in High-side gate driver.

half vs full bridge — Half-bridge vs full-bridge topology comparison

difference between half bridge and full bridge gate driver

Channels & packaging: half-bridge = HS+LS pair (1 IC or two singles); full-bridge = two half-bridges (4 channels).
Timing complexity: full-bridge needs cross-leg synchronization and diagonal conduction prevention; skew compounds across legs.
Thermal & drift: tighter channel-to-channel matching and temperature stability are preferred in full-bridges.

Layout & measurement checklist

Shortest gate/return loop; keep driver ground referenced tightly to the power device (Kelvin source).
Local decoupling near driver pins (small ceramic + bulk).
Separate signal and power routing; avoid long parallel runs between gate traces and power loops.
Plan FAULT/UVLO/EN pull resistors and power-up sequence.
Probe V_GS/GE locally with a differential probe for truthful timing.

What is a gate driver circuit?

The practical arrangement of a driver IC, its supply (bootstrap or isolated), and the gate network (Rg/clamp/snubber) with a tight return path, tailored to a chosen topology (low-side, high-side, half-bridge, full-bridge).

Why do dead-time and delay matching matter?

Mismatch between channels can cause shoot-through or efficiency loss. Use matched drivers with programmable dead-time and verify skew over temperature; see gate driver design.

Further reading: High-side gate driver · Isolated gate driver · Gate driver transformer · Gate driver design

Reference: Wikipedia — Gate driver · MOSFET · IGBT

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High Side Gate Driver

A high side gate driver floats on the switch node (HS) and commonly uses a bootstrap diode + capacitor to power the high-side channel. Bootstrap cannot sustain true 100% duty and is sensitive to dv/dt and power-up transients. If duty-cycle or common-mode noise exceeds the bootstrap window, switch to an isolated gate driver.

Bootstrap operation & limits

Low-side ON creates a recharge window through the diode; high-side ON consumes charge from C_BOOT.
Very high duty, very low frequency, or light load → recharge windows shrink → V_HB droops → UVLO trips or HS gate collapses.
Place the diode, C_BOOT, and driver pins in a tight loop; use fast/Schottky diode and X7R capacitor with derating margin.

Quick sizing — C_BOOT

C_BOOT ≥ (Q_total + Q_leak + margin) / ΔV_allow

Rule of thumb: start with C_BOOT ≈ 10–20 × Q_g(HS), then verify leakage & duty-cycle. Use ΔV_allow=0.2–0.5 V.

Reaching near-100% duty

Duty management: inject short refresh pulses (simple but may not fit tight control specs).
Assisted charge: charge-pump/aux recharge path (limited current and frequency range).
Upgrade path: move to an isolated gate driver/supply for true 100% duty and long static ON time (recommended).

dv/dt robustness & Miller false turn-on

Switch-node dv/dt injects I_Miller ≈ C_gd·(dv/dt) into the gate → false turn-on risk.
Mitigation: Miller clamp, modest negative gate bias, split R_g (faster pull-down), and RC damping/snubber.
Minimize gate/return loop; prefer Kelvin source; select drivers with high CMTI ratings.

Power-up transients & UVLO

Bus ramp and undefined nodes can spur unintended turn-on. Keep the gate hard-pulled down until UVLO thresholds are met.
Sequence EN/FAULT lines; verify thresholds and blanking; measure local V_GS/GE with a differential probe (not at the controller).

Layout & validation checklist

Compact triangle loop: driver pin → diode → C_BOOT → back to driver.
Local decoupling (small ceramic + bulk) right at the driver pins.
Short, direct gate and return; keep away from high-current power loops.
Verify dead-time & propagation skew across temperature; stress-test high dv/dt.
For sustained high duty or static ON, prefer isolated high-side.

Why can’t bootstrap reach true 100% duty?

Bootstrap needs periodic low-side ON time to recharge C_BOOT. With no recharge window, the HS supply droops and UVLO can trip. Use assisted charge or move to an isolated gate driver.

How to stop high-side false turn-on with fast dv/dt?

Use a Miller clamp or slight negative gate bias, split pull-down R_g, add RC damping, minimize gate loop, and pick drivers with high CMTI.

Further reading: Isolated gate driver · Gate driver transformer · Gate driver design · Gate driver fault

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Isolated Date Driver

An isolated gate driver provides signal and/or power isolation with high CMTI, ideal for high-voltage nodes, harsh dv/dt, multi-ground systems, and true 100% duty operation. When bootstrap can’t meet duty-cycle or noise immunity, migrate to an isolated gate driver.

isolated gate driver — isolation levels and CMTI. — Isolation barrier with primary/secondary domains; high CMTI blocks common-mode transients across the barrier.

Why isolated gate driver?

Safety/insulation: meet basic/functional/reinforced insulation needs for human and system safety.
Noise/CMTI: withstand fast switch-node dv/dt (SiC/GaN/IGBT) to avoid false turn-on.
System architecture: break ground loops in multi-module or long-cable designs; support distributed gate power.

CMTI essentials

Definition: Common-Mode Transient Immunity (kV/µs) — immunity to rapid common-mode voltage steps.
Targets (rule of thumb): mainstream MOSFET/IGBT ≥ ~50 kV/µs; SiC/GaN scenarios aim ≥ ~100 kV/µs.
Datasheet reading: rely on minimum spec and test conditions; combine with Miller clamp / negative bias if needed.

Isolation levels (basic / functional / reinforced)

Basic: single insulation for basic protection.
Functional: ensures operation but not necessarily human safety.
Reinforced: single barrier with protection equivalent to double insulation.

Engineer’s checklist: isolation voltage rating, creepage/clearance, lifetime curves, surge/partial-discharge margins versus your target standard.

Two paths to isolation

Isolated gate driver IC: integrated digital isolation; add isolated DC-DC if gate power is needed. Compact and feature-rich.
Gate driver transformer: robust for extreme CMTI/temperature and symmetric drive; requires reset strategy and waveform conditioning.

difference between IGBT and MOSFET gate driver

VDRV: MOSFET commonly +6~10~12 V; IGBT typically +15 V to ensure conduction and minimize loss.
Negative gate bias: MOSFET often 0 V off; high-speed/SiC/GaN may use −2~−3 V. IGBT often uses about −5 V for robust turn-off.
DESAT & soft turn-off: critical for IGBT/SiC short-circuit survival; MOSFET can use other OCP schemes but DESAT is common on IGBT/SiC drivers.

Migrating from MOSFET to IGBT/SiC? Upgrade driver capability: higher V_DRV, negative bias, DESAT/CMTI, and matched timing.

Layout & measurement checklist

Keep primary/secondary loops tight and locally closed; minimize loop areas on both sides of the barrier.
Place isolated power and driver decoupling right at pins.
Short, paired gate/return routing; prefer Kelvin source/emitter packages.
Probe local V_GS/GE with a differential probe to avoid common-mode artifacts.
Provide FAULT/EN lines and a defined soft turn-off path.

Why choose an isolated gate driver over bootstrap?

To achieve true 100% duty, break ground loops, and withstand high dv/dt/common-mode stress with specified CMTI and insulation ratings. See also gate driver transformer for transformer-based isolation.

How much CMTI do I need?

As a rule: mainstream MOSFET/IGBT ≳ ~50 kV/µs; SiC/GaN systems aim ≳ ~100 kV/µs. Validate against datasheet minimum specs and test setups.

Further reading: Gate driver transformer · Gate driver design · Gate driver fault

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Gate Driver Transformer / Transformer Gate Drive

A gate driver transformer (GDT) transfers isolated gate energy via magnetic coupling with extremely high CMTI and harsh EMC tolerance. It excels in symmetric drive and wide temperature ranges, but demands proper reset (demagnetization) and good symmetry—otherwise droop and false turn-on can occur. If you need true 100% duty or long static ON time, consider an isolated gate driver.

gate driver transformer — reset, leakage, symmetry. — Core-driven transformer with primary/secondary windings, reset path, and secondary shaping network for gate drive.

Why use a gate drive transformer?

Extreme CMTI and isolation robustness across long distances and noisy power stages.
Wide temperature / high power suitability versus some capacitive/digital isolation schemes.
System partitioning: break ground loops; support distributed gate power islands.

Need continuous 100% duty or long static ON? Prefer an isolated gate driver with isolated power.

How does a transformer gate drive work?

Flux balance: each primary pulse pushes ΔB; a proper reset path must pull flux back (−ΔB) before the next pulse to avoid core saturation.
Reset strategies: bipolar push-pull (natural reset), dedicated reset winding/diode, or series DC-blocking capacitor + bleed for zero-DC balance.
Wave shaping: secondary clamps (diode/Zener), split R_g, and strong pull-down (or negative bias) to get clean +V_G/0 or +/− gate waveforms.

Design rules (quick)

Drive power: P_drive ≈ Q_g · V_g · f — same entry point as IC drivers.
Turns / core window (avoid saturation): N ≥ V · t_pulse / (ΔB_allow · A_e). Choose ΔB_allow per material; derate for temperature.
Turns ratio: set N_p:N_s for target V_G,ON after losses; verify clamping and shaping margins.
Leakage inductance: interleave/layer windings for tight coupling to speed edges and reduce ringing.
Frequency window: very low f or prolonged duty → reset risk; very high f → leakage and core loss dominate.

Common issues & risks

Insufficient demagnetization → flux walk & saturation → waveform collapse or unintended turn-off.
Poor symmetry → DC bias at the gate → false turn-on or gate overstress.
High leakage → slow edges and heavy ringing; fix layout/winding scheme and add damping.
Weak secondary shaping → turn-off tails/overshoot; add strong pull-down, clamp, or negative bias.

How to make a gate drive transformer (steps)

Collect specs: V_G,ON/V_G,OFF, Q_g, f, allowable droop, ΔB_allow, isolation/CMTI.
Select core/material by frequency & temperature; get A_e and window factor.
Estimate turns: N ≥ V · t_pulse / (ΔB_allow · A_e); refine for droop/leakage.
Plan coupling: interleave/layer; optional shield with awareness of parasitic capacitance.
Secondary shaping: clamp (diode/Zener), split R_g, and optional negative bias; verify rise/fall and overshoot.
Reset strategy: bipolar drive/reset winding/series DC-block; measure flux reset each cycle.
Validate: hot-soak dv/dt, duty edges, long ON tests, short/open gate fault tolerance.

Why choose a gate drive transformer over an isolated driver IC?

For extreme CMTI, wide temperature, high power, or long interconnects. The trade-off is higher design complexity around reset and waveform shaping. If you need continuous 100% duty or long static ON, consider an isolated gate driver.

How do I avoid saturation and waveform droop?

Ensure flux balance with a solid reset path (bipolar/reset winding/DC-block), size turns by N ≥ V·t / (ΔB·A_e), and minimize leakage via interleaving; shape the secondary with clamp and strong pull-down.

Further reading: Isolated gate driver · Gate driver design · Gate driver fault

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Gate Driver for MOSFET

A gate driver for MOSFET (or gate driver circuit for MOSFET) pairs a driver IC with a tuned gate network (split R_g/Miller clamp/snubber) and a tight return path. The goal is to balance EMI and loss: decide target dv/dt / t_r, t_f, then back-solve R_g and drive current.

Quick calcs

I_peak ≈ C_g · (dv/dt)

R_{g_init} ≈ (t_r · V_gate) / I_peak

Then verify driver source/sink current ≥ I_peak and check drive loss P_drive=Q_g·V_g·f (see gate driver design).

MOSFET gate network in 6 steps

Collect Q_g, C_iss/C_rss(≈C_gd), V_th, V_GS ratings, R_DS(on)-vs-V_GS.
Set target edges t_r/t_f or dv/dt (trade EMI vs efficiency/diode recovery).
Estimate I_peak (≈ C_g·dv/dt, or ≈ Q_g/t_r as a shortcut).
Compute R_{g_init} ≈ (t_r·V_gate)/I_peak; start with E12/E24 ladder values.
Use split R_g (up/down): smaller pull-down to strengthen turn-off & Miller immunity; add diode+resistor to shape asymmetry if needed.
Verify driver current and thermal headroom; iterate with bench data (scope local V_GS).

Ringing: diagnosis & mitigation

Minimize loop: keep driver–gate–source (Kelvin source) loop short; avoid parallel runs with power loops.
Shape the network: split R_g, add RC damper or small ferrite bead; consider a gate clamp (diode/Zener) for overshoot.
Measure right: differential probe at the device pins; watch Miller plateau and overshoot.

Miller clamp & negative gate bias

Miller clamp: prioritize for high dv/dt, large C_gd, paralleled devices, or long gate wiring to prevent false turn-on.
Negative bias (≈ −2~−3 V): consider for fast MOSFET/SiC or harsh dv/dt; ensure V_GS(min) margins and driver ratings.
Typical path: start with clamp, then evaluate small negative bias; both can coexist.

Typical MOSFET gate network

Split R_g,up / R_g,down; diode bypass to realize fast-off/slow-on or vice versa.
Optional C_gs/RC damper for high-frequency ringing control.
Gate clamp (Zener/TVS) for transient over-voltage; check leakage and dynamic thresholds.
Shortest Kelvin return and local decoupling at the driver pins.

when to use a gate resistor

Use a gate resistor when edges are too fast (EMI), diode recovery spikes are severe, devices are paralleled, or gate wiring is long/parasitics are high. Reduce R_g when the layout is tight, Q_g is small, and bus voltage is low. Start from R_{g_init} and A/B test a few ladder values.

how to select gate resistor for MOSFET

Follow the 6-step flow above: set dv/dt targets, compute I_peak & R_{g_init}, split pull-up/down, match paralleled gates, and iterate on bench with thermal/EMI observations. Prefer stronger pull-down for Miller immunity.

Layout & validation checklist

Shortest driver–gate–source path; Kelvin source; local decoupling.
Pair gate and return traces; limit vias/series inductance.
Verify t_r/t_f/dv/dt and V_GS overshoot hot/cold; observe the Miller plateau.
Match channels in paralleled devices (R_g, routing symmetry).
Escalate tricky waveforms to gate driver fault troubleshooting.

Further reading: Gate driver design · Gate driver fault

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IGBT Gate Driver

An IGBT gate driver typically uses +15 V turn-on, a modest negative gate bias for turn-off (≈ −5 V), and DESAT detection with soft turn-off to survive short circuits. Provide a reverse (freewheel) diode for current commutation. For high dv/dt/high-voltage stages, prefer an isolated gate driver.

Drive bias & gate control

V_DRV: use about +15 V to reduce conduction loss and ensure strong saturation.
Negative gate bias: ≈ −5 V improves dv/dt immunity and reduces false turn-on; combine with a Miller clamp.
Split R_g: stronger pull-down than pull-up; match channels across paralleled devices.
Layout: Kelvin emitter return, shortest gate/return loop, local decoupling right at the driver pins.

DESAT detection & soft turn-off (core protection)

Principle: sense V_CE via DESAT path; if it exceeds a threshold above normal V_CE(sat), declare a short/hard saturation.
Timing: blanking after turn-on → DESAT threshold trip → soft turn-off to limit dI/dt and over-voltage → fault report/latch.
Engineering knobs: choose threshold with margin over load V_CE(sat); set soft-off slope to avoid over-voltage/thermal stress.
Route DESAT diode/sense lines short and away from high dv/dt nodes; verify behavior hot/cold.

See tuning methods in gate driver design and waveform troubleshooting in gate driver fault.

Reverse current path (freewheel diode)

An IGBT needs a reverse diode for current commutation; select by surge capability, recovery Q_rr, and thermal limits.
Modules may integrate the diode; in discretes, co-design diode and snubbers to manage recovery stress.
Compare to MOSFET: body diode is inherent in MOSFETs, but recovery/EMI still need attention.

Short-circuit & SOA checklist

SC withstand time is typically microseconds-class → DESAT + fast soft-off are mandatory.
Over-voltage control: RC/TVS/active clamp to limit turn-off overshoot.
Fault policy: latch & cooldown before retry; log FAULT status.
Measure local V_GE and V_CE with differential probes; record dI/dt and V_CE peaks.

Layout & measurement checklist

Kelvin emitter reference; short, paired gate/return routing.
Shortest DESAT paths; keep away from switch-node dv/dt fields.
Decouple driver rails at pins (small ceramic + bulk).
Plan FAULT/EN pull resistors and power-up order.
Validate soft-off slope, overshoot clamps, and channel matching over temperature.

is MOSFET better than IGBT

It depends on bus voltage and frequency: low-voltage (≤200–300 V) and high-frequency favor MOSFETs; mid/high voltage (≥600–1200 V) and large currents often favor IGBTs. IGBTs need +15/−5 V, DESAT, and soft-off; MOSFETs emphasize R_DS(on) and gate-charge trade-offs.

can IGBT replace MOSFET

Not pin-to-pin. You must re-evaluate frequency/efficiency targets, add a reverse diode, change drive bias (+15/−5 V), and implement DESAT/soft-off. At low voltage/high frequency, MOSFETs are usually preferable.

why is IGBT used in VFD

Typical VFD buses run ~600–1200 V with moderate switching frequencies and high currents. IGBT modules offer robust conduction, short-circuit survivability (with proper protection), thermal handling, and cost advantages.

why is thyristor not used in an inverter

Thyristors require commutation and have slow turn-off, making high-frequency PWM in modern inverters impractical. IGBT/MOSFET devices suit PWM control; GTO/IGCT are special cases with higher complexity.

Further reading: Isolated gate driver · Gate driver design · Gate driver fault · Gate driver for MOSFET

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Gate Driver Design

Practical gate driver design = timing match (propagation & dead-time) + noise immunity (CMTI, layout) + stable supplies (decoupling/return path) + protections (UVLO/DESAT/soft-off). Decide topology & isolation first, shape the gate network next, then lock layout and measurement.

End-to-end design flow (8 steps)

Inputs: V_BUS, device (MOSFET/IGBT/SiC), Q_g/C_rss, f, efficiency/EMI targets, safety.
Topology & isolation: low/high-side, half/full-bridge, 3-phase; bootstrap vs isolated or GDT.
Driver selection: peak source/sink, CMTI, UVLO, DESAT/soft-off, Miller clamp, channel matching.
Gate network: split R_g, RC damper/ferrite, gate clamp, optional negative bias (see MOSFET section).
Timing: set dead-time; verify t_PLH/t_PHL and channel/temperature mismatch (Δt).
Supply & decoupling: bootstrap sizing or isolated DC-DC; local X7R ceramics + bulk; minimize supply loops.
Protections: UVLO thresholds, DESAT with soft-off ramp, turn-off over-voltage clamps (RC/TVS/active).
Layout & validation: Kelvin source/emitter, tight gate/return loop, differential V_GS/GE probing; hot/cold & high dv/dt stress; escalate oddities to fault.

Timing & dead-time — quick rules

Propagation mismatch: use drivers with tight channel-to-channel skew; target Δt in the few-tens-of-ns class.
Dead-time lower bound: ≥ (max mismatch + diode reverse-recovery window). Too short → shoot-through; too long → diode loss.
Measure at the device: probe local V_GS/V_GE (Kelvin) across temperature; not at the controller pins.

CMTI & isolation choices

Mainstream MOSFET/IGBT aim for ≥ ~50 kV/µs CMTI; SiC/GaN often ≥ ~100 kV/µs.
Harsh dv/dt or multi-ground systems → prefer isolated gate driver or GDT plus Miller clamp/negative bias.

Decoupling & return path (layout)

Place driver decoupling right at pins (multiple small ceramics in parallel + a local bulk cap).
Bootstrap diode and C_BOOT in a compact triangle loop; see high side.
Route gate and return as a paired, short path; avoid long parallel runs with power loops.

what is gate driving loss of MOSFET

Average driver power per channel arises from charging/discharging the gate: P_drive = Q_g · V_g · f. It scales linearly with frequency, gate voltage, and total gate charge, largely independent of load power.

Thermal budget: sum across channels and add driver self-loss; check package θ and copper spreading.
Mitigation: lower Q_g/V_g or split channels; ensure driver peak current meets I_peak while staying cool.
See MOSFET gate network for I_peak/R_g setup.

How do I set dead-time?

Start with (max channel mismatch + diode reverse-recovery window), add safety margin, then tune on the bench over temperature. Measure at the device pins to avoid controller-side illusions.

Further reading: Gate driver for MOSFET · Isolated gate driver · Gate driver transformer · Gate driver fault

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Gate Driver Board

A gate driver board (EVB/prototype) combines the driver IC, isolation/supply, and a tuned gate network on a layout that respects test points, creepage/clearance, ground partitioning, and measurement best practices. Good probing and return-path planning decide whether bring-up is smooth and data is trustworthy.

Board structure & partition

Power / Driver / Control zones separated; slot or keep clearance between HV and LV domains.
Shortest driver–gate–Kelvin source/emitter loop; place return via next to the gate via.
Bootstrap triangle loop (driver pin–diode–C_BOOT) or isolated DC-DC decoupling at pins.

Test points to expose (paired & differential-friendly)

Local V_GS/GE (Kelvin), V_BOOT/V_HB, driver rails (V_DD, V_EE), FAULT/EN.
DESAT node (IGBT/SiC), HS switch node (observe dv/dt alongside gate).
Optional: current shunt/Hall/Rogowski header, thermocouple pads, logic debug header.

Ground planning & return paths

Small-signal driver ground ties to power return via single-point or narrow bridge.
Route gate and return as a paired short path; avoid long parallel runs near power loops.
Keep isolation domains locally closed; do not stitch grounds across the barrier.

Creepage / clearance reminders

Mark HV/LV boundary on silkscreen; reserve no-copper keepouts and avoid vias across the isolation moat.
Size distances per your standard and bus voltage; consider altitude and pollution degree; use slots to boost creepage.
Respect isolation component ratings (basic/functional/reinforced) and follow their layout notes.

Measurement traps (Do / Don’t)

Do use differential probes / coax short ground; Don’t use long alligator ground leads.
Do probe local device pins (Kelvin) for V_GS/GE; Don’t probe at the controller.
Do bandwidth-limit to see the true shape; Don’t misread probe resonances as ringing.
Do observe HS node with V_HB droop; Don’t look at gate alone on high-side debugging.

Bring-up flow (5 steps)

Static checks: UVLO rails, polarity, isolation direction, C_BOOT/diode orientation.
Low-voltage smoke test: reduced rails, no load; verify FAULT/EN, propagation delay.
Single-leg / low duty: ramp frequency/duty; watch V_GS plateau, V_HB droop.
Full-bridge / 3-phase: validate dead-time and inter-leg skew.
Corner cases: hot dv/dt, load steps; record fault behavior and overshoot clamps.

Configurability & safety hooks

Jumpers/DIP: split R_g steps, negative bias on/off, Miller clamp enable, soft-off slope options.
Protection tuning: accessible DESAT threshold/blanking cap; pads for RC/TVS/active clamp.
Safety: HV markings, low-voltage guard area, discharge resistors, interlock header.

BOM notes

R_g ladder (E24/E96), C_BOOT X7R with voltage derating; fast/Schottky diodes.
Drivers with matched channels and high CMTI; isolated DC-DC with pulse-current headroom.

How do I probe V_GS without adding ringing?

Use a differential probe or coax short-ground kit at the device’s Kelvin points; keep the loop tiny and bandwidth-limit the scope if needed.

How much clearance/creepage should I keep?

Size to your standard and bus voltage with margin; consider pollution degree and altitude. Add slots to increase creepage and avoid metal near the barrier.

Further reading: Gate driver design · High-side gate driver · Isolated gate driver · Gate driver fault

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Gate Driver Fault

Typical gate driver faults come from floating gates, ringing & false turn-on, dead-time/skew issues, DESAT trips, insufficient CMTI, and bootstrap sag. Start with correct probing (local differential V_GS/GE + HS node), then use the symptom → cause → action checklist below.

Symptom	Likely causes	Immediate actions	See also
Random turn-on / unstable OFF	Floating gate; weak pull-down; dv/dt-induced Miller injection	Add pull-down; split R_g with stronger down; Miller clamp / slight negative bias	floating gate · MOSFET gate network
Strong ringing / overshoot	Large loop inductance; poor routing; excessive edge speed; snubber missing	Shorten gate/return loop; split R_g; RC damper or ferrite; gate clamp	ringing in MOSFET · design rules
Shoot-through / cross-conduction	Dead-time too short; propagation skew; Miller false turn-on of the opposite device	Increase dead-time; match channels; add clamp/negative bias; verify at device pins	timing & dead-time
DESAT trip / short-circuit events (IGBT/SiC)	Real SC; threshold too low; blanking too short; noisy sense wiring	Tune threshold/blanking; route DESAT short; verify soft turn-off & clamps	IGBT gate driver
High-side drops out at high duty/low f	Bootstrap can’t recharge; V_HB droop; UVLO hit	Assisted recharge; reduce duty; switch to isolated driver	high side · isolated

what happens if a MOSFET gate is floating

A floating gate picks up noise and may randomly turn on, causing heat and EMI. Provide a defined OFF path: add a gate pull-down (≈47–220 kΩ), use stronger pull-down than pull-up, and consider a Miller clamp or small negative bias. See MOSFET gate network and layout rules.

what is ringing in MOSFET

Parasitic L_loop with device capacitances (C_oss, C_gs) forms a resonant tank → visible overshoot/undershoot. Fix with a short paired gate/return loop (Kelvin), split R_g, RC damper or ferrite bead, and an appropriate gate clamp. Probe with a differential head at the pins and bandwidth-limit to avoid “fake ringing.”

why does MOSFET damage / what kills a MOSFET

Usual killers: V_GS over-voltage, V_DS overshoot/avalanche, SOA violation, dv/dt-induced false turn-on leading to shoot-through, thermal runaway, or oscillation. Increase dead-time and channel matching, strengthen pull-down, enable Miller clamp or light negative bias, add over-voltage clamps/snubbers, and optimize layout. See design.

can IGBT block reverse voltage

Standard IGBTs do not reliably block reverse voltage. You typically need a freewheel diode for reverse current. Special RB-IGBTs exist but are uncommon. See IGBT gate driver.

Troubleshooting flow (5 steps)

Reproduce safely: start at reduced rails, single-leg, low duty.
Probe correctly: local V_GS/GE, HS node, V_HB/V_CE, and current dI/dt with proper sensors.
Change one variable: R_g, dead-time, topology element; observe trends.
Identify root cause: if duty/low-f bootstrap sag → switch to isolated driver/fix bootstrap.
Harden: Miller clamp / negative bias / RC damping / layout rework; consider GDT for extreme CMTI.

Measurement Do / Don’t

Do use differential probes or coax short-ground kits; Don’t use long alligator grounds.
Do probe at the device pins (Kelvin); Don’t trust controller-side readings.
Do view HS node with V_HB droop; Don’t look at gate alone on high-side issues.
Do re-test hot/cold; Don’t rely on room-temp only.

Free waveform review (48h)

Upload 3 scope screenshots (local V_GS/GE, HS node, V_HB/V_CE or current) plus BOM/driver/topology. We’ll reply with root-cause ranking, 2–3 immediate fixes, and pin-to-pin alternatives.

Submit screenshots via RFQ

Further reading: Gate driver for MOSFET · IGBT gate driver · High-side gate driver · Isolated gate driver · Gate driver design

Need pin-to-pin alternatives? Submit your BOM — 48h lead-time comparison, compliance & sample-kit suggestion.