Operational Amplifiers: Circuits, Design Limits, and IC Picks

Operational Amplifiers (Op-Amps): Core Circuits & Design Limits

An operational amplifier (op-amp) uses negative feedback to set precise closed-loop behavior. This guide goes beyond definitions—learn inverting and non-inverting circuits, size GBW and slew-rate for real bandwidth, manage rail-to-rail headroom, and ensure stability with capacitive loads. When you’re ready to pick parts, jump to our Selector to shortlist ICs by GBW, SR, offset, noise, and AEC-Q, or submit your BOM for pin-to-pin alternatives and lead-time checks.

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What is an Operational Amplifier (Op-Amp)?

An operational amplifier (op-amp) is a high-gain differential amplifier whose output is proportional to the difference between its two inputs: V_out ∝ (V⁺ − V⁻). With negative feedback and an external resistor/capacitor network, the op-amp’s very high open-loop gain is “tamed” into a precise, predictable closed-loop function (gain, buffer, filtering, summing).

Negative feedback → controlled closed-loop gain

Without feedback, the open-loop gain A₀ is ~10⁵ and impractical. Adding feedback fixes the closed-loop behavior via external components. For a non-inverting stage, the approximate closed-loop gain is A_v ≈ 1 + R_f/R_g. Bandwidth then follows the gain-bandwidth trade-off (see Open-loop & GBW).

+ −

V+

V−

Vout

Op-Amp with Negative Feedback

Aᵥ ≈ 1 + Rf/Rg

Block diagram of an operational amplifier with differential inputs and a negative-feedback network that sets the closed-loop gain.

Ideal vs Real Op-Amp Parameters (typical orders of magnitude)

Parameter	Ideal	Realistic (typical)	Notes
Open-loop gain A₀	∞	2×10⁴–2×10⁵ (≈86–106 dB)	Varies with device and frequency
Input impedance Z_in	∞	CMOS/JFET: MΩ–GΩ; BJT: 100 kΩ–10 MΩ	Choose input type to match source impedance
Output impedance Z_out	0	10–200 Ω (lower in closed loop)	Load current affects swing near rails
Bandwidth / GBW	∞	0.1–50 MHz (general-purpose 1–10 MHz; high-speed ≥50 MHz)	Closed-loop BW ≈ GBW / \|A_v\|
Input offset V_os	0	1 µV–5 mV (zero-drift can <10 µV)	Also check drift (µV/°C)
CMRR	∞	60–120 dB	Resistor matching impacts effective CMR
PSRR	∞	60–120 dB	Important for noisy supplies / ADC drivers

Learn the differential amplifier details → Jump to Design limits (GBW/SR/CMVR) →

Open-loop Response & Gain–Bandwidth Product (GBP)

In an open-loop operational amplifier, the frequency-dependent gain A₀(f) falls roughly at −20 dB/dec (single-pole model). When negative feedback sets a closed-loop gain, the gain–bandwidth product (GBP) is a practical rule of thumb: GBP ≈ |A_v| × BW, so the closed-loop bandwidth scales as BW ≈ GBP / |A_v|. The unity-gain frequency f_T is the point where the open-loop curve meets 0 dB and numerically equals GBP.

60 dB 40 dB 20 dB 0 dB 10 kHz 100 kHz 1 MHz 10 MHz

f_T (GBP)

40 dB (×100) BW ≈ 100 kHz

20 dB (×10) BW ≈ 1 MHz

Open-loop magnitude (concept)

GBP ≈ |A_v| × BW

Open-loop Bode magnitude concept: the unity-gain frequency equals the GBP. A 40 dB closed-loop gain yields ~100 kHz bandwidth for a 10 MHz GBP; 20 dB yields ~1 MHz.

Example 1 — 40 dB gain

Given GBP = 10 MHz and |A_v| = 40 dB (=100), the bandwidth is BW ≈ GBP / |A_v| = 10 MHz / 100 = 100 kHz.

Tip: keep 5–10× headroom versus your highest signal frequency; verify slew rate separately (see Design limits).

Example 2 — 20 dB gain

With the same GBP = 10 MHz and |A_v| = 20 dB (=10), BW ≈ 10 MHz / 10 = 1 MHz.

Note: GBP is a small-signal approximation; multi-pole devices and compensation can deviate—always confirm with the datasheet.

Engineering notes

GBP governs small-signal bandwidth; large-signal behavior is limited by slew rate (check Design limits).
Lower closed-loop gain increases usable bandwidth roughly proportionally, but stability margins and load capacitance still apply.
For full derivations and multi-pole cases, see Op-Amp GBW & Slew Rate.

Core Op-Amp Circuits

External feedback networks turn a high-gain differential core into practical building blocks. Below are five essential operational amplifier circuits—each with its formula, a boundary reminder, and a link to a full tutorial.

Non-inverting

A_v ≈ 1 + R_f/R_g

Inverting

Buffer / Follower

Non-inverting amplifier

Provides voltage gain with very high input impedance, ideal for voltage sources and sensor buffering. The closed-loop gain is set by external resistors, making performance predictable and easy to size for bandwidth via GBP.

Formula: A_v ≈ 1 + R_f/R_g

Boundary: add an input bias resistor R_b and account for input offset V_os being amplified by the closed-loop gain.

Learn more →

Inverting amplifier

Delivers accurate, linear gain with a convenient virtual-ground summing node—great for building adder/summing circuits or precise scaling with known input impedance.

Formula: A_v ≈ − R_f/R_in

Boundary: input impedance equals R_in; large resistor values raise noise and offset error—balance noise, bandwidth, and source loading.

Learn more →

Buffer / Voltage follower

Unity-gain stage for impedance isolation and driving capacitive or sampling loads (e.g., ADC inputs). Protects signal sources from loading effects while preserving amplitude.

Formula: A_v ≈ 1

Boundary: ensure the device is unity-gain stable; with capacitive loads, add an output R_iso (and optional snubber) for stability (see Stability).

Learn more →

Integrator

Implements a −90° phase, −20 dB/dec slope response for signal accumulation, active low-pass behavior, and control loops. Ideal for shaping spectra and extracting slow-varying components.

Formula: V_o = − (1/RC) ∫ V_i dt

Boundary: add a parallel resistor across the capacitor to limit low-frequency drift and set a finite DC gain; verify stability and SR at the highest signal levels.

Learn more →

Differential amplifier

Amplifies the difference between two inputs while rejecting common-mode content—useful for sensor bridges and measurement front ends where CMRR directly impacts accuracy.

Formula: V_o = (R₂/R₁)·(V₂ − V₁)

Boundary: resistor ratio mismatch degrades CMRR; use precision networks or consider an instrumentation amplifier for higher rejection.

Learn more →

Design Limits: Bandwidth, Slew Rate, CMVR/Output Swing, Impedance, Offset

Closed-loop bandwidth is set by the device’s GBW (small-signal), but at higher amplitudes/frequencies the slew rate (SR) becomes the binding constraint. Whether a waveform is even reachable depends on CMVR/output swing relative to supply and load; interface quality follows from input/output impedance; and offset (V_os) & drift govern DC accuracy.

GBW → Closed-loop Bandwidth (small-signal)

After choosing closed-loop gain, estimate bandwidth with BW ≈ GBW / |A_v|. This comes from the open-loop roll-off and the near-constant gain–bandwidth product.

Reality check: multi-pole responses and internal compensation can deviate; confirm with the datasheet and stability analysis.

GBW & derivations →

Slew Rate (large-signal)

For a sine wave, ensure the device can move fast enough:

Criterion

SR ≥ 2π f_max · V_pk

Example

f_max=100 kHz, V_pk=2 V → SR ≥ 2π·100k·2 ≈ 1.26 V/µs.

If SR is insufficient, you’ll see triangle-like tops (slew-limiting). Also verify small-signal BW via GBW.

Review GBW → SR deep dive →

CMVR & Output Swing (reachability)

RR-I (rail-to-rail input) and RR-O (rail-to-rail output) do not mean perfect to-rail. There’s always headroom loss, and it worsens with load current. Validate that your common-mode range covers the input and that the output swing meets the load at both rails.

Supply rails Output headroom (load-dependent)

Rail-to-rail & CMVR details →

Input / Output Impedance

High Z_in: minimizes source loading—prefer CMOS/JFET inputs for high-impedance sensors.
Low Z_out: better drive for following stages/cables; beware capacitive loads that can reduce phase margin.

If you must drive capacitive loads or ADC sampling caps, add output R_iso and check stability.

Stability with C_load →

Input Offset (V_os) & Drift

Offset appears at the output multiplied by closed-loop gain (especially in non-inverting stages). Temperature drift (µV/°C) shifts the DC operating point over time. For millivolt-level signals or long-term accuracy, consider precision / zero-drift devices.

Find precision op-amps → Zero-drift picks → Noise trade-offs →

Quick design checklist

Set |A_v| and estimate BW ≈ GBW/|A_v|.
Verify SR ≥ 2π f_max · V_pk (e.g., 100 kHz/2 V → 1.26 V/µs).
Check CMVR covers input bias; confirm output swing at your load current.
Ensure interface quality: high Z_in, low Z_out; add R_iso for capacitive loads.
Budget V_os and drift; pick precision/zero-drift if DC accuracy matters.

Stability with Capacitive Loads

Capacitive loads add phase lag in the negative feedback loop, reducing phase margin and causing ringing or even oscillation—especially at unity gain (voltage follower). Often you don’t need a new IC: try a small R_iso first.

Compensation #1 — R_iso (+ optional C_snub)

Place a small series resistor at the op-amp output to isolate the capacitive load and restore phase margin. Typical starting values: R_iso=10–33 Ω. If residual peaking remains, add a tiny C_snub=10–47 pF from output to the inverting input to shape the high-frequency feedback.

Validate with 10–100 kHz square-wave steps at near full-scale.
Aim for <10–15% overshoot and critically damped settling.
Recheck thermal rise from added output current into R_iso.

Compensation #2 — Choose “C_load-stable” Devices

Many op-amps are internally compensated to tolerate nF-level loads (often at specific closed-loop gains). This is the simplest route when you can change parts, but expect trade-offs in bandwidth, noise, and quiescent current.

Check datasheet graphs: stable region vs. gain and C_load.
Confirm unity-gain stability if used as a buffer.
Still verify with time-domain tests in your PCB context.

+ −

Vout

R_iso

C_load Load node

C_snub (10–47 pF)

Inverting node

Small series R_iso (10–33 Ω) between op-amp output and the capacitive load improves phase margin; an optional C_snub (10–47 pF) from output to the inverting input further damps peaking.

Stability checklist

Start with R_iso=10 Ω; increase in 5–10 Ω steps until overshoot <10–15%.
If peaking persists, add C_snub=10–47 pF (from output to inverting input) and retest.
Validate with 10–100 kHz square waves at intended amplitude; record overshoot and settling time.
Re-verify GBW/SR margins and thermal impact after compensation.
For frequent buffer use, prefer unity-gain stable or C_load-stable op-amps.

Buffer: unity-gain stability → Back to Design limits → Explore C_load-tolerant op-amps →

Noise Basics: e_n / i_n, Sources, Matching & Bandwidth

An op-amp can be modeled with a series voltage noise e_n and a parallel current noise i_n at its input. Total op amp noise depends on the input structure (BJT/JFET/CMOS), source impedance, the feedback network, and the effective bandwidth. White noise is flat with frequency, while low-frequency 1/f rises below the corner.

e_n, i_n density frequency →

1/f corner

Equivalent input noise density: rising 1/f at low frequency, flat white-noise floor above the corner.

Noise Sources & Spectra

Input e_n/i_n combine with the source and feedback network. Thermal (Johnson) noise of any resistor R contributes √(4kTR) [V/√Hz] and scales with √BW. Many devices exhibit a 1/f rise at low frequencies; the corner frequency varies by architecture.

Key formula

Resistor noise density: v_R = √(4kTR)

Equivalent Input Noise (combine e_n / i_n)

Compare devices by referring all contributors to the input:

V_n,in ≈ √[ e_n² + (i_n·|Z_s|)² + v_R² + … ]

Here |Z_s| is the magnitude of the source impedance; include the thermal noise of source and feedback resistors.

Match Input Type to Source Impedance

High Z_s (≥10 kΩ): prefer JFET/CMOS inputs (very low i_n); reduce feedback resistor values to cut thermal noise.
Low Z_s (≤1 kΩ): prefer BJT (very low e_n); i_n contribution is small with low source impedance.
Middle ranges require trade-offs; always check noise vs. frequency plots in the datasheet.

Input bias current and operational amplifier input impedance also affect DC error and noise gain; consider buffers for very high Z sources.

Bandwidth, Filtering & Total RMS

Total output noise is the integrated noise density over the effective bandwidth of your circuit:

V_n,rms ≈ √∫ S_v(f) · |H(f)|² df

Wider bandwidth → higher noise. Limit BW to what your signal needs or add a front-end RC to reduce integrated noise.

Op-amp noise deep dive →

Practical noise-reduction order

Constrain bandwidth (anti-alias / RC front-end).
Lower resistor values consistent with power/drive limits.
Select a device matched to source impedance (BJT vs. JFET/CMOS).
Optimize layout, grounding, and shielding; minimize loop areas.

Worked Example — 12-bit, 200 kS/s SAR ADC Front-End Buffer (Av = +1)

Goal: drive a 12-bit / 200 kS/s SAR ADC with a unity-gain buffer so the ADC’s sampling capacitor settles within 0.5 LSB. Assume input amplitude example Vpk=2 V (i.e., 4 V_pp worst-case).

Step 1 — Choose topology

Use a voltage follower (buffer) for high input impedance and low output impedance between the signal source and the ADC. The op-amp must be unity-gain stable and tolerant of capacitive loading from the ADC sampling network.

See stability with C_load →

Step 2 — GBW estimate (small-signal)

Rule of thumb for SAR buffers: provide at least 10× the sample rate as gain-bandwidth to handle sampling transients and anti-alias headroom.

Required GBW ≳ 10 × fsample = 10 × 200 kHz = 2 MHz

If PCB/ADC capacitance is large, start with 20× as extra margin. Full derivation: GBW & SR.

Step 3 — Slew-rate check (large-signal)

Ensure the output can move fast enough for the highest tone:

SR ≥ 2π · fmax · Vpk

For fmax=200 kHz and Vpk=2 V → SR ≥ 1.26 V/µs.

Watch for triangular tops on step tests — that’s slew limiting.

Step 4 — Load & stability

The ADC’s sampling capacitor CADC plus PCB stray capacitance form a capacitive load. Add an output Riso=10–33 Ω; if peaking remains, add Csnub=10–47 pF from output to the inverting input.

Compensation recipe →

+ −

Buffer out

Riso

CADC

SAR ADC

Csnub (10–47 pF)

Unity-gain buffer with Riso to the ADC input; ADC sampling capacitor CADC. Optional Csnub from output to inverting input for damping.

Option A — Low-Noise Buffer

For best SNR with moderate/low source impedance.

GBW ≥ 8–10 MHz (ample margin).
SR ≥ 5 V/µs (comfortably above 1.26 V/µs).
en ≤ 5 nV/√Hz (flat), low 1/f corner.
Input: BJT or low-noise CMOS; RR-I/RR-O with small headroom.
Zout low; output current ≥ 30 mA (short bursts).

See low-noise picks →

Option B — Low-Power Buffer

For battery/portable designs where current matters most.

GBW ≈ 2–3 MHz (meets rule-of-thumb).
SR ≥ 1.5 V/µs (≥ 1.26 V/µs requirement).
IQ ≤ 1–2 mA (per channel).
Input: CMOS/JFET for very high Zin, low in.
RR-O to within few tens of mV at target load current.

See low-power picks →

Risk checklist (sign-off)

CMVR (RR-I): input common-mode stays within range across temperature and tolerance?
Output swing: can the buffer reach peaks at the required load current (headroom vs rails)?
GBW/SR: GBW ≥ 2 MHz (or higher) and SR ≥ 1.26 V/µs confirmed on PCB?
Stability: tuned Riso & Csnub; square-wave test overshoot < 10–15%?
PSRR & supply noise: LDO/π filter used if a switching rail feeds the buffer; check layout return paths.

Revisit design limits → Open Op-Amp Selector →

Applications — What is an operational amplifier used for?

Common operational amplifier applications include sensor signal conditioning, active filtering, precision measurement, ADC driving/buffering, and precision rectification or math operations. Pick the topology that fits the job and verify bandwidth, noise, and stability requirements.

Sensor conditioning

Bridge strain gauges, thermocouples, and photodiodes need high input impedance and good CMRR. Use non-inverting, differential, or instrumentation front ends to amplify tiny signals with bias/offset trim and temperature stability.

Recommended: Non-inverting / Differential; for photodiodes use a TIA (transimpedance amplifier).

Non-inverting → Differential →

Active filtering

Build anti-alias, audio EQ, and sensor bandwidth shaping with Sallen–Key, multiple-feedback, or state-variable filters. Op-amp choice must cover GBW and phase margin at the intended Q and gain.

Recommended: Integrator-based topologies; check component tolerance and noise.

Integrator basics →

Precision measurement & amplification

For micro-volt signals, choose high CMRR and low Vos/drift devices. Differential/instrumentation front ends feed DAQ systems while preserving DC accuracy and low noise.

Watch: input bias current, 1/f noise, common-mode range.

Differential basics →

ADC driver / Buffer

Op-amps buffer SAR/ΔΣ ADCs, isolate sources from sampling capacitors, and set level/impedance. Verify GBW, slew rate, output swing, and stability with capacitive loads (Riso + Csnub when needed).

See worked example → Stability tips →

Precision rectifier & math operations

Create precision rectifiers (op-amp + diode) for peak detection and AC measurement without diode drop error. Implement adders, integrators, and differentiators for analog computing and shaping tasks.

Inverting/summing → Integrator →

Op-amp ≠ audio power amplifier. General-purpose op-amps are not suited to directly drive 4/8 Ω speakers (insufficient output current/efficiency). For speaker loads use a dedicated power amplifier (Class AB/D etc.).

FAQ

Fourteen quick answers. Each is concise and links to the relevant section for deeper context.

What is an operational amplifier?

An op-amp is a high-gain differential amplifier whose behavior is shaped by negative feedback. It’s used for signal conditioning, filtering, buffering, math operations, and measurement front ends. Start with fundamentals and symbols in What is an Op-Amp, then browse real-world uses in Applications.

How does negative feedback work?

Feedback returns a portion of the output to the inverting input, converting huge open-loop gain into a precise closed-loop gain, extending bandwidth and improving linearity. Practical limits still apply (GBW, SR, stability). Review the trade-offs in Design Limits and basics in Op-Amp 101.

What is the gain–bandwidth product (GBW)?

In the single-pole small-signal model, the product of closed-loop gain and bandwidth is roughly constant: BW ≈ GBW / |A_v|. Higher gain means lower bandwidth, and vice versa. See examples and a Bode sketch in Open-loop & GBW.

What sets the slew-rate requirement?

Slew rate must exceed the signal’s maximum slope. For a sine: SR ≥ 2π·f_max·V_pk. Insufficient SR causes triangular tops or visible “slew limiting.” See the criterion and numeric example in Design Limits.

Why does my buffer ring with capacitive loads?

A capacitive load adds phase lag in the feedback path, reducing phase margin and causing ringing or oscillation. Add a small series R_iso (10–33 Ω) and, if needed, a tiny C_snub (10–47 pF), or choose a C-load-stable device. Details: Stability with Capacitive Loads.

Inverting vs non-inverting—what’s the difference?

Inverting gain is −R_f/R_in with input impedance equal to R_in; non-inverting gain is 1+R_f/R_g with very high input impedance. Choose by source impedance and summing needs. See formulas and caveats in Core Circuits.

What is a voltage follower used for?

A unity-gain buffer isolates a high-impedance source from a load, drives ADC sampling capacitors, and prevents gain errors from loading. Ensure the op-amp is unity-gain stable and add R_iso for capacitive loads. See Core Circuits and Stability.

Can an op-amp drive 4/8-Ω speakers directly?

No. General-purpose op-amps lack the output current and efficiency required for low-ohmic speakers. Use a dedicated audio power amplifier (Class AB/D) for 4/8-Ω loads. See the clarification under Applications.

What does rail-to-rail really mean?

RR-I (input) and RR-O (output) indicate operation near the rails, but there’s always headroom that varies with load current and temperature. Verify CMVR and output swing in your conditions. More in Design Limits.

What are e_n and i_n in op-amp noise?

e_n is equivalent input voltage-noise density; i_n is input current-noise density. Combined with source impedance and resistor thermal noise, they set total noise over bandwidth. Fundamentals and matching advice live in Noise Basics.

Which input type fits my source impedance?

Low source impedance favors BJT inputs (lower e_n); high source impedance favors JFET/CMOS (very low i_n). Adjust feedback resistor values to reduce thermal noise. See guidance in Noise Basics.

How do I size GBW and SR for a SAR ADC driver?

Use a unity-gain-stable buffer with GBW ≥ 10× sample rate and SR ≥ 2π·f_max·V_pk. Add R_iso (and possibly C_snub) to tame the sampling capacitor. A full walk-through appears in Worked Example.

What are the “golden rules” of ideal op-amps?

The inputs draw no current and sit at equal voltage (via feedback). Real devices deviate due to finite GBW, SR limits, input bias/leakage, offset, and noise. Learn the ideal vs. real parameters in Op-Amp 101 and constraints in Design Limits.

How should I power an op-amp correctly?

Choose supply rails that cover input common-mode and required output swing, then decouple locally and consider PSRR versus your rail noise. Use LDOs or π-filters for sensitive paths. See the CMVR/swing checklist in Design Limits.