Voltage Source Inverter (VSI) IC Guide: Selection & Sourcing

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What is a Voltage Source Inverter (VSI)?

A voltage source inverter (VSI) converts a DC bus, stiffened by a DC-link capacitor, into controlled AC via a three-phase power bridge (MOSFET/IGBT/SiC) and an output filter for grid or motor loads. Typical uses include grid-tied converters, UPS, industrial or traction drives, and energy-storage systems. Modulation (SPWM/SVPWM) sets switching states, while sensing and control synchronize sampling with PWM. In practice, performance and reliability are set by the IC chain: gate-driver, current/voltage sensing & isolation, control MCU/DSP, front-end protection, and auxiliary power. For small batches we support Cut-Tape/Partial Reel supply and pin-to-pin alternatives. Two rules guide later choices: the DC-link voltage level establishes gate-driver CMTI and isolation ratings; and modulation/sampling sync constrains propagation delay, bandwidth, and jitter. Proceed to the IC map and driver specifics below.

Block diagram of a voltage source inverter with DC link, three-phase bridge, and output filter — VSI overview.

Concept	Why it matters to ICs	See section
DC-Link voltage level	Sets CMTI and isolation ratings for drivers/isolators	4.1 Gate Driver ICs · 4.4 Digital Isolation
Two-level vs three-level	Impacts driver timing, desat/soft-turn-off needs	2 Topologies & Modulation · 4.1
SPWM vs SVPWM	Affects sampling bandwidth and isolation delay budget	2 · 4.3 · 4.4
Sampling synchronization	Drives ADC/ΣΔ and isolator jitter/propagation specs	4.3 · 4.4 · 4.2
Front-end protection	Guides pre-charge, eFuse, and ideal-diode choices	4.5 Protection & Front-End

See the IC map → Check gate-drivers →

Topologies & Modulation (2-Level / 3-Level; SPWM / SVPWM)

Two-level vs three-level (NPC/ANPC) — A two-level VSI stresses each device with the full DC-bus and concentrates switching loss, while a three-level NPC/ANPC halves device voltage stress, lowers dv/dt and harmonic distortion, and often allows higher effective switching frequency or efficiency. However, neutral-point control and added devices tighten timing requirements. Three-level bridges typically demand desaturation protection and soft turn-off to survive short-circuit events; isolation ratings and creepage also trend higher. Sampling chains may need wider bandwidth and lower latency to track faster edges and more complex states. IC impact: three-level topologies push gate-driver CMTI/UVLO/desat & soft-turn-off capability and channel-to-channel skew; isolation may require higher VISO/creepage; sensing may need higher BW and lower latency.

Two-level vs NPC inverter topology comparison

Go to Gate Driver →

SPWM vs SVPWM — SPWM is simple but under-utilizes the DC bus and spreads switching unevenly; SVPWM (space-vector) increases DC-bus utilization (~15% gain), shapes harmonic content, and concentrates switching transitions to defined sectors. Both require precise sampling alignment with PWM edges; SVPWM especially raises sensitivity to propagation delay, jitter, and common-mode transients along the isolation path. Your ADC/ΣΔ or isolation amplifier must meet bandwidth and phase-delay budgets set by PWM frequency and current control bandwidth. IC impact: SVPWM elevates demands on digital-isolator CMTI and delay/jitter; the sensing chain (ADC/ΣΔ or isolation amplifier) must satisfy required BW and phase delay for synchronized sampling.

Space vector modulation hexagon and switching states

See Sensing specs → See Digital Isolation specs →

Mapping of inverter topologies/modulation to impacted IC buckets and must-check specs
Topology/Modulation	Impacted IC bucket	Must-check specs	See section
Two-level VSI	Gate Driver	CMTI class, UVLO window, Miller clamp	4.1 Gate Driver ICs
Three-level NPC	Gate Driver & Isolation	Desat/soft-turn-off, channel skew, VISO/creepage	4.1 · 4.4
Three-level ANPC	Driver & Sensing	Skew vs neutral-point control, sensing BW/latency	4.1 · 4.3
SPWM	Sensing	ADC/ΣΔ bandwidth & phase delay vs PWM freq	4.3
SVPWM	Digital Isolation	Delay/jitter & CMTI; sampling sync margins	4.4 · 4.3

From System to ICs (VSI → Six Function Buckets)

A VSI maps cleanly to six IC buckets. Use the function map to navigate: Control MCU/DSP, Gate Driver ICs, Current/Voltage Sensing, Digital Isolation & Isolated Power, Protection & Front-End, and Auxiliary Power. Each bucket below lists must-check specs with typical thresholds, and links to detailed selection tables in Section 4.x.

IC function map for VSI: control, drivers, sensing, isolation, protection, and auxiliary power — IC function map for a VSI.

A. Control MCU/DSP

PWM resolution / HRPWM: sets current-loop ripple → typical 12–16-bit or HRPWM step < 10 ns.
ADC sync & throughput: align sampling to PWM → synchronous trigger, ≥1–2 MSPS, simultaneous sampling preferred.
Three-level support: timing/dead-time complexity → prefer native libraries/app notes.
Control latency budget: ISR + sampling + compute → within tens of µs per bandwidth target.

Go to details →

B. Gate Driver ICs

CMTI: immunity to common-mode transients → 2-level ≥ 50–100 kV/µs; 3-level/SiC ≥ 100–150 kV/µs.
Peak source/sink current: gate charge vs loss → 2–8 A typical; higher for SiC.
Desat & soft turn-off: survive short-circuit → detect + act ≤ 1–2 µs with controlled slope.
Channel skew / UVLO window: symmetry & safety → skew < 50 ns; UVLO matched to device.

Go to details →

C. Current/Voltage Sensing

Bandwidth & phase delay: loop response/THD → motor control needs ~100–300 kHz effective BW; minimize delay/phase error.
Linearity & drift: accuracy stability → ±0.5–1% FS with low tempco preferred.
CMR / input range: survive noise/common-mode → CMRR high; range fits bus/shunt location.
Isolation option: Hall vs iso-amp/ΣΔ → choose by dynamics, precision, and system isolation plan.

Go to details →

D. Digital Isolation & Isolated Power

VISO & creepage: safety/standards → 2.5–5 kVrms classes as required.
Propagation delay & jitter: sync & dead-time → delay ~10–30 ns; jitter ~1–3 ns.
CMTI & channel count: dv/dt immunity & density → ≥100 kV/µs; channels by drive/sense/comms plan.
Isolated power POUT & ripple: gate-side bias → 0.5–2 W typical, low ripple/EMI.

Go to details →

E. Protection & Front-End

Current limit accuracy (ILIM): predictable protection → ±5–10% typical.
dv/dt control & reverse protection: inrush/surge/reverse → integrated dv/dt; ideal-diode/ORing control.
Load-dump / ISO 7637-2 readiness: transient survivability → select per pulse profile/energy.
Pre-charge coordination: DC-link soft-start → time constants ~50–500 ms with thermal checks.

Go to details →

F. Auxiliary Power

VIN max & cold-crank: input limits/dips → design for automotive 12 V or 24/48 V industrial rails.
Fsw & EMI features: noise/efficiency trade-off → 200–600 kHz typical; spread-spectrum/soft-switching preferred.
Current limit / thermal: fault behavior → peak limit/foldback/thermal shutdown.
Noise / PSRR (LDO): analog/ADC friendliness → low-noise tens of µV_rms.

Go to details →

Quick navigation map of VSI functions with key specs, roles, risks, and section links
Function	Key Specs	Typical role in VSI	Risk notes	See section
Control MCU/DSP	HRPWM, ADC sync, latency	FOC/SVPWM & grid control	Latency budget often underestimated	Go to details · Check lead-time
Gate Driver ICs	CMTI, Ipk, desat/soft-off	Safe switching & fault handling	Skew/UVLO mismatches kill devices	Go to details · Check lead-time
Sensing (I/V)	BW, phase delay, drift	Current loop & protection	Under-bandwidth = lag & noise	Go to details · Check lead-time
Digital Isolation / Isolated Power	VISO, delay/jitter, CMTI	Data/drive across isolation	Jitter breaks sampling sync	Go to details · Check lead-time
Protection & Front-End	ILIM, dv/dt, reverse	Inrush, surge, reverse events	Ignore load-dump at your peril	Go to details · Check lead-time
Auxiliary Power	VINmax, Fsw, EMI	Bias & control rails	Ripple injects control noise	Go to details · Check lead-time

4. IC Selection Guide (Six Function Buckets, Deep Dive)

Each sub-section follows the same structure: (a) selection points & thresholds, (b) representative series (seven major brands), (c) alternatives mapping (pin/function/timing notes), (d) small-batch sourcing notes (AEC-Q, packages, Cut-Tape/Partial Reel, Date Code/COC), and (e) internal links & micro-CTAs. All master tables share the same columns to simplify CSV maintenance.

4.1 Gate Driver ICs (IGBT / SiC / MOSFET)

Gate Driver ICs catalog → Check lead-time →

CMTI: 2-level typically ≥ 50–100 kV/µs; 3-level/SiC often ≥ 100–150 kV/µs.
Peak source/sink: 2–8 A typical; match to Q_g and target rise/fall times.
Desat & soft turn-off: detect + act ≤ 1–2 µs; controllable soft-off slope.
UVLO (on/off) window: prevent half-turn-on; match MOSFET/IGBT thresholds.
Channel-to-channel skew: bridge symmetry; target < 50 ns.
Miller clamp / gate shaping: suppress false turn-on; reduce EMI.
Isolation & creepage: select VISO/creepage per DC-bus and safety class.

Function	Brand	Series/PN	Key Specs (CMTI/Ipk/Delay/UVLO…)	AEC-Q	Package	Pin-to-Pin Notes	Typical Use in VSI	Alternatives	Stock/MOQ Hint	Datasheet URL
Gate Driver	TI	UCC21520 / UCC21520-Q1	High CMTI; ~4A pk; dual-channel; UVLO; Miller clamp	Yes (Q-grade options)	SOIC-WB	Y — timing & pinout differ vs STGAP2S	2-level/3-level bridge high/low-side	STGAP2S; NCD57000	Cut-Tape / Partial Reel	link
Gate Driver (SiC/IGBT)	TI	UCC2173x (desat/soft-off)	Desat; soft-off; high CMTI; OV/UV protections	Options	SOIC-WB/QFN	N — function-compatible class; layout differs	SiC/IGBT legs with fast protection	GD3160; MIC46xx	Partial Reel	link
Gate Driver	ST	STGAP2S / L639x family	Isolated/half-bridge; UVLO; Miller clamp; fast edges	Options (-Q)	SOIC-WB/TSSOP/QFN	N — not pin-compatible with UCC21520	BLDC/FOC; 2-level bridges	UCC21520; NCD57000	Cut-Tape	link
Gate Driver (SiC/IGBT)	NXP	GD3160 (desat/soft-off)	High-voltage isolated; desat; soft-off; robust UVLO	Yes (-Q)	SOIC-WB/QFN	N — function-compatible vs UCC2173x class	SiC traction/industrial legs	UCC2173x; MIC46xx	Partial Reel / Tray	link
Pre-driver / 3-phase	Renesas	HIP4086 (3-phase pre-driver)	3-phase bootstrap; timing control; robust gate options	Varies	TSSOP/QFP (var.)	N — not pin-compatible to isolated drivers	Low-/mid-voltage 3-phase BLDC	L639x; MCP14E**	Cut-Tape	link
Gate Driver	onsemi	NCD57000 series	Isolated; high CMTI; strong peak drive; protections	Options (NCV)	SOIC-WB	N — timing/pins differ vs UCC21520/STGAP2S	2-level/3-level legs	UCC21520; STGAP2S	Partial Reel / Reel	link
Gate Driver / Buffer	Microchip	MCP14E** / MIC46xx	Non-isolated buffers; strong drive; flexible rails	Varies	SOIC/TSSOP	N — for isolated stages pair with 4.4 power/iso	Low-side / pre-driver buffering	HIP4086; L639x	Cut-Tape	link

Primary	Alt-1	Alt-2	Notes (Pin/Timing/CMTI)	Package
UCC21520	STGAP2S	NCD57000	Not P2P; check input logic, delay, CMTI class	SOIC-WB
UCC2173x	GD3160	MIC46xx	Desat/soft-off strategy & thresholds differ	SOIC-WB/QFN
L639x	HIP4086	MCP14E**	Pre-driver class; bootstrap & timing details differ	TSSOP

Sourcing notes: prefer Q-grade variants where applicable; SOIC-WB/QFN for creepage/thermal; keep external gate-resistor range in BOM. Small runs supported via Cut-Tape / Partial Reel; request Date Code & COC in the BOM form.

4.2 Control MCU/DSP (SVPWM / FOC / Grid)

Motor/Power Control MCU → Request sample kit →

PWM resolution / HRPWM: 12–16-bit or sub-10 ns step for low ripple.
ADC sync: hardware-triggered, simultaneous sampling; ≥1–2 MSPS.
3-level support: native dead-time/state-machine & library support.
Latency budget: ISR + sampling + compute within tens of µs.
ASIL/AEC-Q100 & ecosystem: libraries/examples/toolchains.

Function	Brand	Series/PN	Key Specs (PWM res/ADC sync/CPU MHz/HRPWM/ASIL)	AEC-Q	Package	Pin-to-Pin Notes	Typical Use in VSI	Alternatives	Stock/MOQ Hint	Datasheet URL
Control MCU/DSP	TI	C2000 (TMS320F2800x/28004x)	HRPWM; fast ADC sync; motor/grid libraries	Options (Q1)	LQFP/QFP	N — ecosystem alignment matters	FOC/SVPWM, grid-tie control loops	STM32G4; dsPIC33C	Cut-Tape / Eval kits	link
Control MCU	ST	STM32G4 / F3 (Motor control)	Advanced timers; ADC sync; rich motor libs	Options	LQFP/QFN	Partial pin-compat across STM32 families	BLDC/FOC control; power conversion	C2000; dsPIC33C	Partial Reel / Eval kits	link
Control MCU/DSP	Microchip	dsPIC33C (Digital power/motor)	Motor/power libraries; robust PWM/ADC sync	Varies	QFN/TQFP	N — migrate by code/toolchain	Low-to-mid power VSI control	C2000; STM32G4	Cut-Tape / Eval kits	link
Control MCU (Auto)	NXP	S32K family	Automotive grade; timers/ADC for motor/power	Yes (AEC-Q100)	LQFP/QFN	N — family-specific pin maps	Automotive inverter control	RX24T/RA6T2; C2000	Tray / Partial Reel	link
Control MCU (Motor)	Renesas	RX24T / RA6T2	Motor control IP; ADC sync; fast PWM	Options	LQFP	N — migration within family feasible	FOC/SVPWM on 2-/3-level topologies	S32K; STM32G4	Cut-Tape / Eval kits	link

Primary	Alt-1	Alt-2	Notes (Tools/Lib/HRPWM)	Package
C2000	STM32G4	dsPIC33C	Library & HRPWM features differ; porting effort	QFP/QFN
S32K	RX24T/RA6T2	C2000	Auto grade & libs vary; re-verify timing	LQFP

Sourcing notes: prioritize packages your EMS can rework (LQFP/QFN), order evaluation kits with first spins, and specify minimum lots for prototypes. We support Cut-Tape / Partial Reel.

4.3 Current/Voltage Sensing & Isolation

Current Sensors → Isolation Amplifier/ADC → Check lead-time →

Bandwidth & phase delay: motor loops ~100–300 kHz effective BW; minimize delay/phase error.
Linearity & drift: ±0.5–1% FS typical with low tempco for stable torque/control.
CMR & input range: high CMRR; input range fits bus/shunt location.
Topology choice: Hall vs isolation amplifier/ΣΔ per dynamics/precision/isolation plan.
ΣΔ rate/interface: align modulator rate & decimation with MCU timing.

Function	Brand	Series/PN	Key Specs (BW/Linearity/CMR/Delay/Range)	AEC-Q	Package	Pin-to-Pin Notes	Typical Use in VSI	Alternatives	Stock/MOQ Hint	Datasheet URL
Isolation amplifier / ΣΔ	TI	AMC130x family	High CMRR; low delay; options for ΣΔ/analog out	Options (-Q1)	SOIC-WB/SSOP	Family-level drop-ins; check gain/range	Phase current / DC-bus sensing	MCP3911; ISL26134; MLX9122x (Hall alt)	Cut-Tape	link
Hall current sensor	Melexis	MLX9120x / MLX9122x	High-accuracy Hall; fast response; wide ranges	Options (AEC-Q)	SOIC/SIP (var.)	N — mechanical window differences	Phase/bus current with isolation by physics	AMC130x; ISL26134 (ΣΔ)	Partial Reel	link
ΣΔ ADC (multi-channel)	Microchip	MCP3911 / family	ΣΔ front-end; flexible interfaces; metering heritage	Varies	TSSOP/QFN	N — timing/DR filters differ vs AMC family	Phase currents / bus voltage (ΣΔ chain)	AMC130x; ISL26134	Cut-Tape	link
ΣΔ ADC / isolator alt	Renesas (Intersil)	ISL26134 / ISL28xxx family	High-resolution ΣΔ; low drift; robust CMR handling	Options	TQFP/QFN	N — interface modes differ	Precision sensing & metering-style chains	MCP3911; AMC130x	Cut-Tape / Tray	link
Current sense amplifier	ST	TSC101 / TSC2010 (example)	High-side sensing; gain options; simple front-ends	Varies	SOIC/TSSOP	N — gain pinouts differ	Low-side/bus current, non-isolated	NCS21x (onsemi); MCP6N11 (Microchip)	Cut-Tape	link

Primary	Alt-1	Alt-2	Notes (BW/Delay/CMR)	Package
Hall (MLX9122x)	Isolation amp (AMC130x)	ΣΔ ADC (ISL26134)	Dynamics vs precision trade-offs; isolation strategy differs	SOIC/SSOP
ΣΔ (MCP3911)	AMC130x	ISL26134	Interface/decimation change affects sampling sync	TSSOP/QFN

Sourcing notes: confirm temperature grade; SOIC-WB/SSOP solderability; for Hall parts check mechanical window and routing. We support Cut-Tape / Partial Reel for prototypes.

4.4 Digital Isolation & Isolated Power

Digital Isolators → Isolated Power → Check lead-time →

VISO & creepage: choose 2.5–5 kVrms class per standards & bus voltage.
Propagation delay & jitter: aim ~10–30 ns delay, ~1–3 ns jitter for sampling sync.
CMTI & channels: ≥100 kV/µs class; select channel count per drive/sense/comm.
Isolated power: 0.5–2 W typical; low ripple/EMI to keep drivers quiet.

Function	Brand	Series/PN	Key Specs (VISO/CMTI/Delay/Jitter/Channels/POUT)	AEC-Q	Package	Pin-to-Pin Notes	Typical Use in VSI	Alternatives	Stock/MOQ Hint	Datasheet URL
Digital isolator	TI	ISO77xx family	High VISO/CMTI; low delay/jitter; multi-channel options	Options (-Q1)	SOIC-WB/SSOP	Family drop-ins possible; verify channel mapping	PWM, ADC sync, comms across isolation	ISL3274x; STISO621	Cut-Tape	link
Digital isolator	Renesas	ISL32741E / ISL32704E family	Robust CMTI; low delay; high-isolation GMR tech	Options	SOIC-WB	N — pinouts vary vs ISO77xx	Fast digital links and PWM signals	ISO77xx; STISO621	Partial Reel	link
Digital isolator	ST	STISO621 / STISO62x family	High VISO; strong CMTI; compact channel mixes	Options (-Q)	SOIC-WB/SSOP	N — verify logic polarity & channel order	Gate/MCU signals across isolation	ISO77xx; ISL3274x	Cut-Tape	link
Isolated power (module/driver)	TI	UCC12050 / SN6505A	0.5–2 W class; transformer-driver option; low ripple features	Options	SOIC/QFN	N — magnetics differ by design	Bias rails for high/low sides	Alt iso-power from catalog	Cut-Tape / Partial Reel	link

Primary	Alt-1	Alt-2	Notes (Delay/Jitter/VISO)	Package
ISO77xx	ISL32741E	STISO621	Not P2P; match logic polarity & timing budget	SOIC-WB
UCC12050	SN6505A + transformer	Alt iso-power (catalog)	Different magnetics & EMI behaviors	SOIC/QFN

Sourcing notes: confirm insulation rating & creepage; align isolator delay/jitter with sampling sync; plan magnetics for isolated power. Cut-Tape / Partial Reel available for proto lots.

4.5 Protection & Front-End (eFuse / Ideal-Diode / High-Side / Pre-charge)

eFuses → Ideal Diode / ORing → High-Side Switches → Submit partial reel →

ILIM accuracy: ±5–10% typical; choose foldback vs latch-off per risk profile.
dv/dt control & reverse: inrush/soft-start, reverse-battery & backfeed protection.
Load-dump / ISO 7637-2: verify pulse profile/energy against device limits.
ORing / ideal diode: current sharing & forward drop for multi-source rails.

Function	Brand	Series/PN	Key Specs (ILIM/dvdt/Rev-prot/TSD/ISO7637-2)	AEC-Q	Package	Pin-to-Pin Notes	Typical Use in VSI	Alternatives	Stock/MOQ Hint	Datasheet URL
eFuse (Hot-swap)	TI	TPS2598x / TPS27xxx	Adjustable ILIM; dv/dt control; fault logging options	Options (-Q1)	QFN/TSSOP	N — package/ILIM pins vary	Front-end inrush & fault control	STEF01; NIS5xxx	Cut-Tape / Partial Reel	link
Ideal-Diode / ORing	TI	LM74800-Q1 (controller)	Reverse-battery, backfeed control, fast ORing response	Yes (Q1)	VQFN	N — verify gate/MOSFET pairing	Reverse/ORing on input rails	ISL614x; NIS5xxx	Partial Reel	link
eFuse	ST	STEF01 / family	Programmable ILIM; surge handling; protections suite	Options (-Q)	QFN/TSSOP	N — not P2P vs TPS2598x	Front-end protection/inrush	TPS2598x; NIS5xxx	Cut-Tape	link
Hot-swap / ORing	Renesas (Intersil)	ISL614x family	ORing control; surge ride-through; telemetry options	Options	QFN/TQFN	N — pin variants across family	Datacenter/industrial ORing or input	LM74800-Q1; NIS5xxx	Tray / Partial Reel	link
eFuse / High-side switch	onsemi	NIS5xxx / NCV84xxx	eFuse & protected high-side families; thermal/OC features	Options (NCV)	SOIC/QFN	N — electrical equivalence varies	Pre-charge/soft-start/OC protection	TPS27xxx; STEF01	Reel / Partial Reel	link

Primary	Alt-1	Alt-2	Notes (Logic/ISO7637-2)	Package
TPS2598x	STEF01	NIS5xxx	Not P2P; ILIM/dvdt pins & protections differ	QFN/TSSOP
LM74800-Q1	ISL614x	NIS5xxx (controller alt)	ORing response & FET sizing differ; verify surge	QFN

Sourcing notes: confirm ISO 7637-2/load-dump targets; check thermal pad & copper area; request samples for pre-charge tuning. Cut-Tape / Partial Reel supported.

4.6 Auxiliary Power (Buck / LDO)

Buck Converters → LDO Regulators → Check lead-time →

VIN max & cold-crank: match 12/24/48 V rails; handle dips/surges appropriately.
Fsw & EMI: 200–600 kHz common; benefit from spread-spectrum/comp options.
Current limit / thermal: peak limit, foldback, thermal shutdown behavior.
Noise / PSRR (LDO): keep analog/ADC rails quiet; low-noise choices for sensing chains.

Function	Brand	Series/PN	Key Specs (VINmax/Fsw/EMI/ILIM/η/Noise)	AEC-Q	Package	Pin-to-Pin Notes	Typical Use in VSI	Alternatives	Stock/MOQ Hint	Datasheet URL
Buck regulator	TI	LMR33630 / LMR36006 (example)	Wide VIN options; high-efficiency; spread-spectrum variants	Options (-Q1)	SOT-23/QFN	Family variants differ in pinout	Controller/driver bias rails	A6986x (ST); MCP16331	Cut-Tape	link
Buck regulator (Auto)	ST	A6986x / L7987 (example)	Automotive-ready; EMI features; robust transients	Yes (-Q)	HTSSOP/QFN	N — compensation & pin maps differ	Bias rails for gate drivers/MCU	LMR33630; NCP3170 (onsemi)	Partial Reel	link
Buck regulator	Microchip	MCP16331 / family	Compact; internal FET; easy BOM for aux rails	Varies	SOT-23/DFN	N — check EN/PG pin behavior	Low-power control rails	LMR33630; A6986x	Cut-Tape	link
LDO (low-noise)	onsemi	NCV1117 / family (example)	Automotive LDOs; moderate PSRR; simple biasing for analog rails	Yes (NCV)	SOT-223/TO-252	N — pin config may differ vs TI/ST	ADC/amp rails (noise-tolerant)	TPS7Axx (TI); LDL/LDL1117 (ST)	Reel / Partial Reel	link
LDO (precision/low-noise)	TI / ST (example)	TPS7Axx / LDL/LDL1117	Low noise; good PSRR for sensing/ADC rails	Options	SOT-23/SOIC	N — verify pinouts and dropout specs	Sensitive analog domains	NCV11xx; MCP17xx	Cut-Tape	link

Primary	Alt-1	Alt-2	Notes (EMI/Noise/Pin)	Package
LMR33630	A6986x	MCP16331	Different comp/EN pins; EMI features vary	SOT-23/QFN
TPS7Axx	LDL/LDL1117	NCV1117	Pinouts/dropout vs noise specs differ	SOT-23/SOT-223

Sourcing notes: plan magnetics for bucks early; specify EMI goals (spread-spectrum, filters); choose low-noise LDOs for sensing rails. Prototype orders supported with Cut-Tape / Partial Reel.

5. Mini Reference Designs (Small-Batch / Prototype)

Two “minimum-closed-loop” BOMs you can order for quick bring-up. Each maps directly to the 4.x buckets and uses Cut-Tape / Partial Reel friendly parts.

A | 48 V / 1–2 kW 3-Phase BLDC (2-Level, MOSFET)

Get the sample kit →

A practical 48 V inverter baseline using isolated dual drivers, Hall or isolated-amp sensing, low-delay digital isolation, and a Buck→LDO rail set. Optimized for small batches with Cut-Tape / Partial Reel options.

Path: Protection & Front-End → Gate Driver → Sensing (I/V) → Digital Isolation → Aux Power → Control MCU

CMTI: target ≥ 50–100 kV/µs for 2-level (see 4.1)
Peak drive (Ipk): ~4–6 A depending on Q_g and target rise/fall (4.1)
Sensing BW / delay: ~100–300 kHz effective BW, minimize phase delay (4.3)
VIN / Fsw (Buck): 48 V rail; 200–600 kHz with EMI options (4.6)

Function	Part (Brand)	Why here	Key Specs to check	Alternatives	MOQ/Packaging
Protection (eFuse/Hot-swap)	TPS2598x (TI)	Controlled inrush & current limit	ILIM, dv/dt, TSD	STEF01, NIS5xxx	Cut-Tape
Ideal-Diode / ORing	LM74800-Q1 (TI)	Reverse battery & backfeed control / ORing	Reverse, ORing response, FET sizing (4.5)	ISL614x	Partial Reel
Gate Driver (isolated dual)	UCC21520 (TI)	High-CMTI dual for HS/LS legs (MOSFET)	CMTI 50–100 kV/µs, Ipk ≈4 A, UVLO, skew	STGAP2S, NCD57000	Cut-Tape
Phase Current (Hall)	MLX9122x (Melexis)	Fast Hall chain with inherent isolation	BW, drift, mechanical window	— or — AMC130x (iso-amp)	Partial Reel
Phase/Bus Sense (iso-amp)	AMC1301/AMC130x (TI)	High CMRR, low delay alternative to Hall	CMRR, delay, gain range	ISL28xxx, MCP3911 (ΣΔ)	Cut-Tape
Digital Isolation	ISO77xx (TI)	Low delay/jitter for PWM & sampling sync	VISO, delay/jitter, CMTI	ISL32741E, STISO621	Cut-Tape
Isolated Power (driver bias)	UCC12050 / SN6505A (TI)	0.5–1 W bias with low ripple options	POUT, ripple/EMI, transformer choice	Other iso-power in 4.4	Partial Reel
Buck (48→12/5 V)	LMR33630 (TI)	Wide VIN, compact, EMI features available	VINmax, Fsw, EMI	A6986x, MCP16331	Cut-Tape
LDO (analog rails)	TPS7Axx (TI) / LDL (ST)	Low noise PSRR for ADC/amps	Noise, PSRR, dropout	Alt: NCV11xx	Cut-Tape
Control MCU/DSP	C2000 / STM32G4 / dsPIC33C	HRPWM + synchronous ADC sampling	PWM res, ADC sync, latency	Alt: S32K, RX24T	Eval kit + Cut-Tape

Sample kit tip: 1–2 pcs per line; mix SOIC-WB/QFN where available; request Date Code & COC in the BOM form. More details in 4.1, 4.3, 4.4, 4.6, and 4.5.

B | 400 V-Class Three-Level NPC Skeleton (IGBT/SiC Drive)

Get the sample kit →

A high-voltage three-level NPC IC combination only: fast desat + soft-turn-off drivers, ΣΔ isolated sensing, high-CMTI digital isolation, isolated bias, and a coordinated front-end with pre-charge.

Path: Front-End & Pre-charge → Three-Level Gate Drive → ΣΔ Sensing → Digital Isolation & Isolated Power → Control MCU

Safety note: This skeleton lists IC combinations and layout principles only; no live-voltage parameters or test procedures are provided.

Function	Part (Brand)	Why here	Key Specs to check	Alternatives	MOQ/Packaging
Pre-charge / Hot-swap	TPS27xxx (TI) eFuse class	Controlled pre-charge & surge management	ILIM, dv/dt, surge profile	STEF01, ISL614x	Partial Reel
Ideal-Diode / ORing	LM74800-Q1 (TI)	Reverse protection & source ORing	Reverse tolerance, ORing dynamics (4.5)	ISL614x	Partial Reel
3-Level Gate Driver (desat/soft-off)	UCC2173x (TI) / GD3160 (NXP)	Short-circuit survival & high CMTI for IGBT/SiC legs	Desat ≤2 µs, soft-off slope, CMTI ≥100–150 kV/µs	Alt buffer: MIC46xx	SOIC-WB / Partial Reel
Neutral-point / clamp driver	UCC21520 (TI) / STGAP2S (ST)	Mid-point legs with tight skew & UVLO	Skew <50 ns, UVLO window, clamp options	NCD57000	Cut-Tape
ΣΔ Isolated Current Sense	AMC130x (TI)	Low delay, high CMRR, ΣΔ interface to MCU	BW/Delay, CMR, ΣΔ rate/decimation	ISL26134, MCP3911	Cut-Tape
Bus Voltage Sense (iso-amp)	AMC1301 (TI)	Stable gain and isolation for DC-link sensing	Gain, CMR, delay budget	Alt: ISL28xxx	Cut-Tape
Digital Isolation (PWM/Sync)	ISO77xx (TI)	High CMTI, low jitter for SVPWM sync	VISO, delay, jitter, channels	ISL32741E, STISO621	Cut-Tape
Isolated Power (per-leg bias)	UCC12050 / SN6505A (TI)	0.5–2 W isolated rails for each driver side	POUT, ripple, transformer/EMI plan	Other iso-power (4.4)	Partial Reel / Tray
Aux Buck (front-end)	A6986x (ST) / LMR33630 (TI)	Front-end bias & iso-power pre-reg	VINmax, Fsw, EMI	MCP16331	Cut-Tape
Control MCU/DSP	C2000 / S32K / RX24T	3-level timing, SVPWM libs, ADC/PWM sync	HRPWM, ADC sync, latency	Alt: STM32G4 / dsPIC33C	Eval kit + Cut-Tape

Sample kit tip: 1–2 pcs per line; prioritize multiple driver options (desat/soft-off); mix SOIC-WB/QFN; specify Partial Reel / Tray. More details in 4.1, 4.3, 4.4, 4.5, and 4.6.

6. Layout & EMC Checklist (Getting to Production)

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Push frequent layout/EMC pitfalls up-front so IC choices and parameters land correctly on Rev A. Each item maps a physical practice to specific IC specs (from 4.x) so you can align the PCB, components, and measurements before fab.

A. Power Stage & Gate

Gate loop area & symmetry — shrink loop inductance and ringing across both legs. Related IC spec: Ipk, rise/fall time, CMTI. See: 4.1 Gate Driver ICs
Kelvin source return — separate power return from gate sense to avoid false turn-off/on. Related IC spec: UVLO window, Miller clamp strength. See: 4.1
Miller coupling & clamp — manage dv/dt-induced turn-on with clamp/shaping. Related IC spec: CMTI class, Miller clamp, soft turn-off. See: 4.1
Desat diode routing — shortest, quietest path back to driver; avoid delay & nuisance trips. Related IC spec: Desat response time, soft-off slope. See: 4.1
DC-link placement & shortest loops — stack caps/planes to minimize switching loop area. Related IC spec: CMTI margin, isolation VISO/creepage. See: 4.4 Digital Isolation

B. Sensing & ADC

Shunt Kelvin sense — take sense leads off inner pads; keep power current out of measurement loop. Related IC spec: Bandwidth, phase delay, CMRR. See: 4.3 Sensing
Hall window & routing — avoid core saturation & stray fields; orthogonal return paths. Related IC spec: Linearity, temp drift, usable BW. See: 4.3
Anti-alias & timing sync — RC/LC where needed and align sample instants with PWM. Related IC spec: ΣΔ rate/decimation, isolator delay/jitter. See: 4.3, 4.4
ADC ground star point — single-point return near ADC/iso-amp to limit ground modulation. Related IC spec: CMRR, PSRR, input range. See: 4.3

C. Isolation & EMC

Isolator channel skew & jitter — verify PWM & sampling alignment under noise. Related IC spec: Propagation delay, jitter, CMTI. See: 4.4
Creepage/clearance — match to bus voltage & standards; respect package height. Related IC spec: VISO rating, creepage (mm). See: 4.4
Spread-spectrum strategy — clock spreading on bucks where allowed to tame peaks. Related IC spec: Fsw, EMI features. See: 4.6 Aux Power
CM/DM filtering placement — put filters at noise sources; avoid re-excitation by long leads. Related IC spec: dv/dt, CMTI class. See: 4.5 Front-End, 4.4

D. Front-End & Power

Inrush / pre-charge path — stage the DC-link ramp; keep sense refs quiet during ramp. Related IC spec: ILIM accuracy, dv/dt control, ISO 7637-2 pulses. See: 4.5
Reverse/ORing layout — tight loop around FETs; Kelvin to controller sense pins. Related IC spec: Reverse tolerance, backfeed limit, gate drive interface. See: 4.5
Isolated power magnetics — shield/return selection and spacing to driver loops. Related IC spec: POUT, ripple, EMI. See: 4.4, 4.6

E. Thermal & Mechanical

Thermal path & vias — size copper and via arrays for steady-state & pulses. Related IC spec: Driver Ipk vs gate losses; package θJA/θJC. See: 4.1
Bulk/decap ESL/ESR choice — mix values to catch wideband ripple & spikes. Related IC spec: dv/dt stress, CMTI headroom, front-end stability. See: 4.5

Layout & EMC Mini Table

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Checklist item	Why	Related IC spec	See section
Gate loop area & symmetry	Reduce L and ringing across both legs	CMTI, Ipk, tr/tf	4.1
Kelvin source return	Prevent false turn-on/off via source inductance	UVLO, Miller clamp	4.1
Desat diode routing	Short, quiet path for fast protection	Desat time, soft-off slope	4.1
DC-link stacking & shortest loops	Shrink switching loop and CM noise	CMTI margin, VISO/creepage	4.4
Shunt Kelvin sensing	Keeps load current out of measurement loop	BW, phase delay, CMRR	4.3
Hall window placement	Avoid saturation and stray field pickup	Linearity, drift, BW	4.3
Anti-alias & sync with PWM	Maintain phase coherence for SVPWM/FOC	ΣΔ rate, isolator delay/jitter	4.3, 4.4
ADC ground star point	Reduce ground-bounce at ADC/iso-amp	CMRR, PSRR, input range	4.3
Isolator skew & jitter control	Keep PWM & sampling aligned under noise	Delay, jitter, CMTI	4.4
Creepage & clearance budgeting	Meet safety vs bus voltage & pollution degree	VISO, creepage (mm)	4.4
Spread-spectrum on bucks	Reduce peak emissions without heavy filtering	Fsw, EMI options	4.6
CM/DM filter placement	Filter close to sources; avoid long stubs	dv/dt, CMTI	4.5, 4.4
Inrush / pre-charge path	Control DC-link ramp & protect upstream rails	ILIM, dv/dt, ISO 7637-2	4.5
Reverse/ORing loop minimization	Fast ideal-diode response; lower stress	Reverse tol., backfeed limit	4.5
Thermal path & via arrays	Keep junction temps in check under pulses	Driver Ipk vs losses; θJA/θJC	4.1

Need a second set of eyes? Use the button above for a quick layout/EMC review. For spec deep-dives see 4.1 Gate Driver, 4.3 Sensing, 4.4 Digital Isolation, 4.5 Front-End, and 4.6 Aux Power.

7. Qualification & Compliance (Automotive/Industrial & Transients/ESD)

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Standards only help when translated into IC choices and receiving documents. This section aligns engineering and purchasing: map AEC/ISO/ESD to concrete specs (e.g., CMTI, VINmax, ILIM, HBM/CDM), then request COC, test reports, and Date Code/Lot/MSL on the PO.

AEC-Q100 / AEC-Q101

Device classes: ICs (gate drivers, isolators, MCUs, bucks/LDOs) fall under AEC-Q100; discrete FETs/diodes/TVS in the front-end typically follow AEC-Q101. See: 4.1 Gate Driver, 4.6 Aux Power, 4.5 Front-End.
Temperature grades: Grade 0/1/2 map to −40–150/125/105 °C; use them as selection gates for drivers, supplies, and controllers.
Burn-in/HTOL & ESD labels: require HBM/CDM ratings on the datasheet and evidence of HTOL/Burn-in as part of the qualification summary.
Traceability: receiving must record Date Code / Lot / MSL; request COC per shipment.

ISO 7637-2 & Load-Dump (Automotive Supply Transients)

Pulses 1/2a/2b/3a/3b: convert waveforms into IC checks: ILIM accuracy, dv/dt control, reverse/ORing capability, thermal shutdown/foldback. See 4.5 Front-End.
Load-Dump (12/24 V systems): validate VINmax, surge tolerance, and EMI strategy of bucks/LDOs (spread-spectrum, snubbers, input networks). See 4.6 Aux Power.
Documentation: ask for ISO 7637-2 test summaries or manufacturer statements and include COC + Date Code in the PO notes.

ESD (Device-Level & System-Level)

Device-level: require HBM (JEDEC JS-001) and CDM (JS-002) ratings for drivers, digital isolators, MCUs, and iso-amps. See 4.4 Digital Isolation, 4.1 Gate Driver.
System-level: plan board/connector protection to meet IEC 61000-4-2 / ISO 10605; ties back to front-end TVS, ideal-diode, and ground strategy. See 4.5 Front-End.
Receiving: request ESD test summaries and anti-static packaging labels; record Date Code/Lot/MSL.

Functional Safety: Redundant Over-Current/Over-Temp Chain

Combine a fast desaturation trip with soft turn-off in the gate driver (hard stop), a precise ΣΔ/iso-amp feedback to the MCU (diagnostics), and a firmware shutdown path. Check Desat ≤1–2 µs, soft-off slope, isolation delay/jitter, and MCU fault GPIO logging. See 4.1, 4.3, 4.4, 4.2.

Compliance Mapping Card

Include these in my shortlist →

Standard	Affected IC bucket	Must-have spec/label	Doc to request (COC/Report)	See
AEC-Q100 Grade 1 (HBM/CDM noted)	Gate Driver	Grade 1 label; CMTI class; HBM ≥2 kV; CDM ≥500 V	COC + AEC-Q100 report + Date Code/Lot/MSL	4.1
AEC-Q100 Grade 0 (High-temp)	Aux Power (Buck/LDO), MCU/DSP	−40–150 °C rating; VINmax; Fsw/EMI options; HRPWM/ADC sync (MCU)	COC + AEC-Q100 summary + Date Code/Lot	4.6, 4.2
AEC-Q101 (front-end discretes)	Protection & Front-End	Reverse/ORing capability; surge/thermal ratings aligned with controller IC	COC + AEC-Q101 + Date Code/Lot	4.5
ISO 7637-2 Pulses 1/2a/2b/3a/3b	Protection & Front-End	ILIM accuracy; dv/dt control; reverse/backfeed protection; TSD/foldback	COC + ISO 7637-2 test summary	4.5
Load-Dump (12/24 V)	Aux Power (Buck/LDO)	VINmax margin; surge withstand; EMI/spread-spectrum options; cold-crank behavior	COC + Surge/Load-Dump report + Date Code	4.6
ESD HBM (JS-001) / CDM (JS-002)	Digital Isolation, Gate Driver, MCU, Sensing	HBM ≥2 kV; CDM ≥500 V; input pin classes noted; VISO where applicable	COC + ESD report + Date Code/Lot/MSL	4.4, 4.1, 4.3
IEC 61000-4-2 / ISO 10605 (System ESD)	Protection & Front-End, Digital Isolation	TVS selection; path to chassis/returns; isolator CMTI headroom	System ESD test summary + COC	4.5, 4.4
Functional safety (OC/OT redundant chain)	Gate Driver + Sensing + MCU	Desat ≤1–2 µs; soft-off slope; ΣΔ/iso-amp delay/jitter; MCU fault GPIO/log	COC + vendor safety app-notes	4.1, 4.3, 4.2
Creepage/Clearance & VISO	Digital Isolation, Sensing (iso-amp/ADC)	Package creepage (mm); insulation class; VISO rating vs DC-link	COC + insulation rating statement	4.4, 4.3
MSL & Handling (J-STD-020 / -033)	All IC buckets	MSL level; bake/handling; tape/reel/tray labeling	COC + packing spec + Date Code/Lot/MSL on labels	4.6, 4.1, 4.5

Purchasing tip: include COC / AEC or ISO 7637-2 test summaries / ESD report / Date Code / Lot / MSL in your PO line notes. For part selection, jump to 4.5 Front-End, 4.6 Aux Power, and 4.1 Gate Driver.

8. Troubleshooting (Typical Faults → IC Actions)

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Start from symptoms and backtrack to the IC bucket and parameter you should change. Each case links to the relevant selection guides (4.x) and the Layout & EMC checklist (6) so you can act before the next spin.

Case 1 — Shoot-Through

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Symptoms: leg overheating, blown fuses, bus dip; gate waveforms show double-pulses or a high Miller plateau.
Quick checks: scope HS/LS gates vs source, deadtime setting, channel propagation skew, Miller plateau position.

Root cause

IC: Driver Ipk too low / UVLO window mismatch; missing/weak Miller clamp; excessive channel skew. (4.1 Gate Driver)
Layout: Large/asymmetric gate loop; Kelvin source not separated; long/noisy desat path. (6)

IC buckets to adjust: Gate Driver (4.1), Digital Isolation (4.4), MCU (4.2)

Change these: raise CMTI class (≥100–150 kV/µs), increase R_g,on, enable Miller clamp, set soft turn-off, tighten skew, tune deadtime.

Shoot-through diagnosis: HS/LS gate timing and Miller plateau — Shoot-through waveform cues.

Case 2 — Over-Current False Trip

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Symptoms: protection at light load; desat node noisy; ΣΔ input shows spikes.
Quick checks: desat diode routing/return, blanking time, ΣΔ rate/decimation, comparator threshold/hysteresis.

IC: improper desat response/blanking; iso-amp/ΣΔ insufficient BW/Delay; drifting comparator threshold. (4.1, 4.3)
Layout: desat loop coupled to switch node; shunt not Kelvin. (6)

IC buckets to adjust: Gate Driver (4.1), Sensing (4.3)

Change these: Desat ≤1–2 µs, appropriate blanking, ΣΔ rate/decimation, iso-amp CMRR/Delay, comparator hysteresis/RC.

Case 3 — dV/dt Interference

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Symptoms: digital isolation glitches; PWM jitter; MCU oversampling anomalies.
Quick checks: isolator CMTI, propagation delay/jitter; HS dv/dt; ground bounce; snubber presence.

IC: isolator CMTI too low or jitter high; driver common-mode release. (4.4, 4.1)
Layout: large DC-link loop; iso-power magnetics return/shielding not controlled. (6)

IC buckets to adjust: Digital Isolation (4.4), Gate Driver (4.1)

Change these: move to higher CMTI class (≥100–150 kV/µs), lower delay/jitter; modestly increase R_g,on, add RC snubber, enable spread-spectrum on bucks (4.6).

Case 4 — Sensor Saturation

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Symptoms: current/bus readings rail; FOC divergence; protection thresholds drift.
Quick checks: iso-amp input/common-mode range, front-end gain/divider, input clamps; Hall window flux density.

IC: iso-amp range exceeded; ΣΔ dynamic range too small; ADC ref/bit-depth insufficient. (4.3)
Layout: divider routing pickup; Hall position causing core saturation. (6)

IC buckets to adjust: Sensing (4.3), Aux Power (4.6)

Change these: re-set CMR/input range, recompute gain/divider; add TVS/limit at front-end; match ADC FSR/reference.

Case 5 — EMI Fail at Compliance

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Symptoms: conducted/radiated bands over limits; front-end resets or comms dropouts.
Quick checks: buck/driver Fsw & harmonic clusters, spread-spectrum setting, LC/CM choke placement, loop areas.

IC: buck lacks spread-spectrum; driver edges too fast; iso-power ripple high. (4.6, 4.1, 4.4)
Layout: CM/DM filter too far; harness coupling; missing ground segmentation/Single-Point tie. (6)

IC buckets to adjust: Aux Power (4.6), Gate Driver (4.1), Digital Isolation (4.4)

Change these: enable spread-spectrum, retune Fsw, add RC/RC-snubber, moderate R_g, optimize iso-power POUT/ripple.

Problem → Action Card

Send my waveforms/logs →

Issue	Root cause (IC/layout)	IC bucket to adjust	Spec/setting to change	See section
Shoot-Through	Low Ipk, weak/no clamp; big/asymmetric gate loop	Gate Driver; Digital Isolation	CMTI↑; R_g,on↑; enable clamp; soft-off; skew↓; deadtime tune	4.1, 6
Over-Current False Trip	Desat/blanking mis-set; ΣΔ/iso-amp BW/Delay; shunt not Kelvin	Gate Driver; Sensing	Desat ≤1–2 µs; blanking; ΣΔ rate/decim; CMRR/Delay; add hysteresis	4.3, 6
dV/dt Interference	Isolator CMTI low/jitter high; DC-link loop large	Digital Isolation; Gate Driver	CMTI≥100–150 kV/µs; delay/jitter↓; R_g,on↑; snubber; spread-spectrum	4.4, 6
Sensor Saturation	Iso-amp CMR/input exceeded; ΣΔ dynamic range small; divider pickup	Sensing; Aux Power	CMR/input range; gain/divider; front-end clamp; ADC FSR/ref	4.3, 6
EMI Fail	No spread-spectrum; driver edges fast; iso-power ripple; filters too far	Aux Power; Gate Driver; Digital Isolation	Enable spread-spectrum; Fsw retune; RC/RC-snubber; R_g tune; iso-power ripple↓	4.6, 6

Need targeted substitutions? Post your scope shots and current BOM via the buttons above. For background, see 4.1 Gate Driver, 4.3 Sensing, 4.4 Digital Isolation, 4.6 Aux Power, and 6 Layout & EMC.

9. FAQs

Quick answers to common queries, each linking to the deeper section for specs, thresholds, and small-batch (Cut-Tape / Partial Reel) guidance.

What’s the difference between a VSI and a CSI?

A VSI holds a stiff DC-link and shapes the voltage, while a CSI regulates current with a large series inductor. VSI dominates motor drives/UPS/grid-tie because it pairs well with PWM and standard gate-driver ICs. CSI suits niche high-current cases. For IC selection, VSI emphasizes driver CMTI/peak current and sampling delay/jitter budgets. See modulation/topology trade-offs and how they map into drivers, sensing, and isolation before you pick parts.

See Chapter 2 (Topologies & Modulation).

Two-level vs. three-level (NPC/ANPC) — how should I choose?

Choose two-level for simplicity and cost; choose three-level (NPC/ANPC) when you need lower device stress, lower THD, or higher efficiency at medium–high voltages. Three-level raises requirements on gate-driver timing skew, desat/soft-off, and sensing bandwidth. It can also tighten isolation delay/jitter tolerance. Start from bus voltage and efficiency target, then confirm driver CMTI/timing and ΣΔ/iso-amp bandwidth to match your PWM frequency and deadtime strategy.

See Chapter 2 and driver details in 4.1.

SVPWM vs. SPWM — which is better and why?

SVPWM improves DC-bus utilization and reduces harmonic content versus SPWM at the same switching frequency. The trade: tighter requirements on propagation delay/jitter and channel-to-channel skew for isolation/driver paths, plus ADC sampling alignment. If you chase acoustic/EMI limits or want more torque per volt, pick SVPWM and verify isolator CMTI/jitter and MCU ADC–PWM sync at your target Fsw and deadtime.

See Chapter 2 and isolation specs in 4.4.

For small batches, which ICs should I buy first for a VSI?

Prioritize: gate drivers (with CMTI/UVLO/desat/soft-off), current/voltage sensing (Hall or iso-amp/ΣΔ), digital isolation, and bias supplies (isolated power + buck/LDO). These unlock bring-up and protect hardware even before final control tuning. Order sampleable packages with Cut-Tape / Partial Reel options and keep an A/B driver and sensor on hand to de-risk. Use our mini reference BOMs as your starting basket.

See Chapter 5 (Mini Reference Designs) and 4.1.

How do I grade gate-driver CMTI and peak drive current?

Set CMTI ≥50–100 kV/µs for typical 2-level MOSFET stages; target ≥100–150 kV/µs for fast SiC/3-level legs. Size peak drive current from device total gate charge and your desired rise/fall times (often 4–6 A for mid-power MOSFETs, higher for SiC). Confirm UVLO windows, soft turn-off, Miller clamp, and channel skew to match your deadtime and dv/dt plan.

See Chapter 4.1 (Gate Driver ICs) and layout advice in 6.

Hall sensor vs. isolated amplifier — when should I pick each?

Use Hall when you want inherent isolation, simple mechanics, and moderate bandwidth with minimal insertion loss. Choose shunt + isolated amplifier/ΣΔ when you need tight linearity, phase control, and higher bandwidth for FOC/grid-tie. Verify common-mode range, delay/phase, and drift; Hall placement must avoid saturation and stray fields, while shunt must be Kelvin-sensed with clean returns.

See Chapter 4.3 (Sensing & Isolation) and layout in 6.

Do I need digital isolation? Which specs matter most?

Yes, whenever control, sensing, or comms cross high dv/dt domains or safety boundaries. Prioritize insulation rating (VISO/creepage), CMTI versus your dv/dt, propagation delay/jitter (for PWM/ADC sync), and channel count. For high-speed SVPWM/3-level, small jitter and matched skew prevent duty distortion and false trips. Pair with an isolated bias supply sized for driver and sensing rails.

See Chapter 4.4 (Digital Isolation & Isolated Power) and 6.

How do I fix EMI failures quickly?

First, enable spread-spectrum on bucks if available, then retune switching frequency away from problem bands. Add/trim RC snubbers at the switch node, moderate gate resistors to slow edges, and move CM/DM filters close to noise sources with short returns. Check isolated power ripple/shielding and confirm single-point ground ties near ADC/iso-amp.

See Chapter 4.6 (Auxiliary Power) and 6.

What documents should purchasing request for compliance?

Ask vendors for a COC plus AEC-Q100/101 summaries (as applicable), ESD HBM/CDM ratings, and ISO 7637-2 or surge test summaries for front-end and bucks. Require Date Code/Lot/MSL on labels, and note Cut-Tape / Partial Reel packaging on the PO. This ensures traceability and accelerates receiving and audit steps for pilot runs.

See Chapter 7 (Qualification & Compliance).

What causes shoot-through and how do I stop it?

It’s usually insufficient deadtime, weak/absent Miller clamp, low driver peak current, or excessive channel skew—often amplified by large/asymmetric gate loops. Increase R_g,on modestly, enable soft turn-off and clamp, tune deadtime, and improve Kelvin source routing. When using SiC/3-level, move to higher-CMTI/low-jitter isolation to avoid spurious timing errors.

See Chapter 8 (Troubleshooting) and 4.1.

10. Submit Your BOM

Submit BOM → Ask lead-time →

Within 48 hours you’ll receive a lead-time comparison, pin-to-pin alternatives, a compliance check (AEC-Q / Industrial), and a sample-kit suggestion tailored for small-batch builds. We support Cut-Tape / Partial Reel, and can capture Date Code and provide COC upon request.

Typical use cases: 48 V BLDC prototypes, 400 V NPC skeleton validation, and second-source onboarding.
Deliverables include footprint/timing risk notes and compliance flags aligned to your environment.

BOM review flow: lead-time comparison, compliance, pin-to-pin alternatives, risks — BOM review flow: lead-time, pin-to-pin, compliance, risks.

What you get in 48h

Service	What you get in 48h	Notes (COC/Date Code/Packaging)
Lead-time comparison	Brand A/B/C current availability & ship windows	Add Date Code capture in PO; Cut-Tape/Partial Reel options shown
Pin-to-Pin alternatives	Footprint/timing cross with risk notes (spec deltas)	Packaging choices: Partial Reel / Tray; advise on MSL handling
Compliance check	AEC-Q / Industrial flags, ESD (HBM/CDM) & ISO 7637-2 relevance	Attach COC & test summaries; label requires Date Code / Lot / MSL
Sample-kit suggestion	A/B drivers & sensors for quick bring-up (small-batch friendly)	Prefer Cut-Tape/Partial Reel to minimize MOQ

Submit your BOM (48-hour response)

Company / Project (optional) Contact Email *

Target Time Window * Partial Reel (Cut-Tape) acceptable?

BOM Upload (CSV/XLSX/PDF) (recommended) Tip: if you skip upload, please paste the inline BOM below. Inline BOM (paste rows as: Brand | Part Number | Qty | Notes) Provide either an upload or the inline BOM (one is enough).

AEC-Q required? AEC-Q Grade (if applicable)

Need a sample-kit suggestion?

Compliance docs needed COC Date Code Lot MSL

Notes (links to waveforms/layout, environment, constraints)

Privacy note: we’ll only use your data to prepare the 48-hour response. You can request deletion at any time.

Ask lead-time →

After submission: “Thank you — your BOM is queued. Expect our 48-hour response with lead-time, pin-to-pin, and compliance notes.”

Need examples before submitting? See Chapter 5 (Mini Reference Designs). For document requirements, see Chapter 7; for waveform-guided advice, see Chapter 8.